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ref-ddr-sdram-vhdl
- 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
ref-sdr-sdram-verilog
- 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
1076 IEEE Standard VHDL Language Reference Manual.
- 1076-2002 IEEE Standard VHDL Language Reference Manual-1076-2002 IEEE Standard VHDL Language Ref validated Manual
ref-ualaw
- A率/u率 压缩与解压缩的IP核,。 # 由AHDL语言写成,可在MaxplusII和QuartusII中使用,源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
very-good-ok-ref-ddr-sdram-verilog
- Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
ref-sdr-sdram-verilog
- sdram的控制器 verilog源码
vhdl.ref
- vhdl是硬件系统描述语言,本书详细介绍了此语言的具体内容。
ref-sqroot
- 開平方根IP將sqroot_license.txt中的FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING=gl15kdhm5gUPkJD7iM82mn$$ HOSTID=ANY加入就可以使用了!
ref-sdr-sdram-vhdl
- 标准SDR SDRAM控制器参考设计_verilog_lattice\\sdr_ctrl.v
ref-sdr-sdram-verilog
- SDRAM的vegilog代码,做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
ref-sdr-sdram-verilog
- 标准SRD SDRAM控制器参考设计,altera提供 Verilog代码,带有使用手册,大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
ref-ddr-sdram-vhdl
- 基于VHDL编写的DDR-SDRAM控制器的编程,目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
ref-sdr-sdram-vhdl
- 基于VHDL编写的SDR-SDRAM控制器的编程,目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
ref-sqroot
- 这是用于VHDL的开方运算,大家试试看,能不能好用-sqrt
ref-sdr-sdram-verilog
- SDRAM控制器,使用verilog编写-SDRAM controller, use the write verilog
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
ref-sdr-sdram-verilog
- sdram的verilog 建模参考设计,希望有所帮助-sdram and verilog implent
ref-sqroot
- 求平方根的ip核,Altera提供,可以用在FPGA上,是AHDL语言写的,不开放源码-Square root of the ip seeking nuclear, Altera provides, can be used in FPGA, is written in AHDL, not open source
vmodcam-ref-vga-demo-12
- 通过fpga(注:xilinx公司的板子)从vmodcam取数据并用vga显示。-vmodcam ref vga demo