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6_VHDL-application-design
- VDHL应用实例，包括组合逻辑电路设计，时序逻辑电路设计，存储器设计，状态机设计 -VDHL application design samples, including combined logic design, timing logic design, memory design, and status machine design
FPGA_ADC7513_DAC7822
- 芯片：cyclonge ii ep2c35f484c8 功能：NCO产生0-200K的扫频信号，并经过穿行DADA7513输出。 再经过串行ADC7822采样，用singaltap II 比较输入和输出的波形-Chip: cyclonge ii ep2c35f484c8 function: NCO generates 0-200K sweep signal, and after a walk through DADA7513 output. Then after serial ADC7822
V_ADC_SPCTR_ANALZ
- Including the design of high-speed AD sampling and analysis of all source code, can be directly applied to samples of the actual signal AD.
VHDL-program--samples-book
- VHDL程序实例集，其主要内容包括：用VHDL设计的组合电路、时序电路、数字综合电路、电路图输入法要领概述、实用VHDL语句等。-VHDL instance set, the main contents include: VHDL design of combinational circuits, sequential circuits, digital integrated circuit schematic input method essentials outlines, practica
FSKPSK
- 本方案需要设计有100个单元的查找表，其中每个单元分别保存100个正弦波采样的对应样值。-This project needs to design to have checking of 100 unitses to seek form, among them, each unit keeps 100 sine wave samples respectively of to be worth in response to the kind.
QDEC
- 旋转编码器的正交解码程序，使用VHDL语言--- This decoder in VHDL samples the signals using all four available edges of -- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on -- falling(A), and sample(A) on rising(B).
chuankoushoufa
- 接收代码: 对接收数据的采样频率：16X9600HZ 接收代码编写思路： 首先判断起始位,没有数据传输时，起始位为“1”的状态，当有数据时起始位为“0”。因为采样的频率是通信频率的16倍，所以当连续8次（数据位正中间）采集为“0”时就认为是有数据到来。那么可以开始采集数据位，以后每隔16个脉冲采集一个数据（每个数据的正中央，不易发生畸变的部分），连续采样8次，即完成数据位的采集。最后实现串并转换。如此重复即可。（因为通信已经预约好，停止位和校验位都为“1”，不会对数据产生影响。）
Verilog-Accumulator
- the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a te
RS(204-188)decoder
- rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。 仿真波形：
AD7606PFSM
- AD7606利用状态机进行模拟时序控制采样。-AD7606 using the state machine to simulate timing control samples.
protel99
- elecfans.com-protel 99 se常用元件封装， protel99se基础教程，Protel99SE快捷键大全，分立元件库图形样本，工程师应该掌握的20个模拟电路等基础知识。-Protel 99 se commonly used components encapsulation, based tutorial protel99se, protel99se shortcuts, discrete component library graphic samples, the engi
Nexys4FFTDemo-master
- A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT output