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arm9_fpga2_verilog
- ARM9的开发源代码，全套，很难得。 现全部共享。-ARM9 development of source code, a full set, it is difficult to get. Are all shared.
3Channel_CIS_Processor_with-VHDL.ZIP
- This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by
seg
- 用VHDL编写的数码管显示程序（数码管共用数据线），带有进制转换功能-Written in VHDL, digital tube display program (digital control shared data line), with a binary conversion
arm9_fpga2_verilog
- ARM9的开发源代码，全套，很难得。现全部共享。 -ARM9 development of source code, complete, very rare. Are all shared.
fpga111
- 基于FPGA步电机毕业设计的开通报告，共享给大家，希望有用-Step Motor Based on FPGA opening graduation report, shared with us the hope that useful
fortye_lib
- protel 及AltiumDesigner库,大部份在含有3D元器件 本人自己整理及收藏 对于使用AD及protel的人会有个不小的收获 现分享给大家-protel and AltiumDesigner library, most of my own finishing with 3D components and collections for the use of AD and protel people have not a small gain is shared for
dpram_anu
- true dpram with using shared variable
ce
- 51单片机程序代码可以共享，需要的继续练习-51 microcontroller code can be shared
BPSK
- 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.
vhdl-simple-computer
- implementation of simple computer (alu, shared bus, register, input and output)in VHDL language and an example of assembly code is present with complete descr iption
vga_lcd_latest.tar
- vga lcd 控制器 24位VGA控制，支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
ca_code_VHDL
- 本程序是ca码的FPGA产生程序，希望在此能够给与大家共享-This program is ca code generated by FPGA program, I hope to give everyone shared this
uart_trs_state
- 本程序是串口的FPGA产生程序，希望在此能够给与大家共享-This program is a serial FPGA generator, I hope to give everyone shared this
8051core-Verilog
- 用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！-Verilog FPGA internal 8051 core, super, super hard to find! Shared out!
a
- VHDL编写的一个简单的8位全加器，提供分享-VHDL prepared a simple 8-bit full adder, providing shared
DE2_115_Audio
- This a shared & storage file, which was written by Altera. It is quite possible that Applications will use this sample.-This is a shared & storage file, which was written by Altera. It is quite possible that Applications will use this sample.
router_five_port
- On-chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions of router area and pow
第2章_Quartus_II_使用方法
- I hope the PDF file I shared is very useful for your work. Thanks
第2章_Quartus_II原理图输入
- I hope the PDF file I shared is very useful for your job. Thanks