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SPI串口的内核实现spicore
- SPI串口的内核实现spicore SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore
s_pandp_s
- 用VHDL编写的并串转换和串并转换实例，希望对您有所帮助，其中输入数据是时钟的16倍-prepared using VHDL and string conversion and string conversion and examples, and I hope to help you, the input data which is 16 times the clock
txt_util
- VHDL的字符串处理函数库，含数字与字符串之间的转换-VHDL string handling functions, containing figures and the conversion between the strings
pa_ser
- 这是我自己写的4位并转串ISE代码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!
pn_code
- 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog pro
jdcbzh.使用VHDL语言实现串并转换模块的实现
- 使用VHDL语言实现串并转换模块的实现，可在QUARTUS上实现,Use VHDL language string and conversion module, but in QUARTUS
IS-95/CDMA2000基带成形滤波器的实现
- IS-95/CDMA2000基带成形滤波器的实现 IS-95滤波器的实现： 本次设计采用转置型结构，并用展开技术将字串行架构转换成字并行处理架构，从而提高运行的速度。本次设计中采用展开因子J=4的展开转换技术。设输入数据为filter_in，输出数据为filter_out，则其展开因子J=4的并行处理系统如下图所示 ,IS-95/CDMA2000 base-band filter shaping to achieve IS-95 filter to achieve: the desig
bsconvert
- 基于FPGA的实现数据串并转换的程序，可以把8位串行数据转换为8位并行数据，或把8位并行数据转换为8位串行数据等-FPGA-based string and data conversion procedures, can be 8-bit serial data into 8-bit parallel data, or the 8-bit 8-bit parallel data into serial data
uart.rar
- Verilog编写的UART程序源代码。测试成功。支持字符串发送,UART prepared Verilog source code. Successful test. Support string sent
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
vhdl.rar
- 74ls164 8位移位寄存器 串入并出,74ls164 8-bit shift register and a string into
p2s
- 并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.
SHFRT4_1
- 四位串入并出移位寄存器,实现串并转换,已通过时序验证-Four series in and out of shift register, to achieve string and conversion, has passed the timing verification
uartfifo
- 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
chuan2
- 用verilog HDL编写的并串转换模块，在ISE软件仿真过，也可综合-Prepared using verilog HDL and string conversion module, in the ISE software simulation, and can also be integrated
1
- 串并滤波器(FPGA源码),基于QuartusII开发设计实现的串并滤波器.-String and filter (FPGA source code), based on the achievement of development and design of QuartusII and filter string.
8aqm-string-and-convert-vhdl-program
- 8aqm调制串并转（1:3）换部分vhdl程序-8aqm string and convert vhdl program
String-and-conversionVERILOG
- 该压缩文件包含一个verilogHDL实现数据的串并连转换功能。-Use verilog realize string and even the conversion function
4-a-string-and-converter
- 4 位串并转换器 vhdl语言 描述-4 a string and converter VHDL language describe
the-design-of-string-out-of-register
- 利用FPGA编程-------实现“并入串出寄存器设计”-Use of FPGA programming-------incorporated into the design of string out of register