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convolution_encoder_VHDL
- 卷积码编译码,由SERVICE、PSDU、TAIL和PAD域组成的DATA域应进行卷积编码，码率应根据所需的传输速率从R=1/2,2/3,3/4中选择-for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
vtbird_21
- 雷鸟车尾灯状态机,vhdl实现，对学习VHDL的同学有帮助。-Thunderbird taillights state machine, vhdl realize, the study has helped students VHDL.
CMOS_Low_PhaseNoise971103
- RF CMOS Low-Phase-Noise LC Oscillator Through Memory Reduction Tail Transistor
viterbidecoder
- viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
qicheweideng
- 汽车尾灯控制电路 左右各3个指示灯。向一侧转弯时，指示灯循环点亮。刹车时，指示灯全亮-Car tail lights control circuit around the three indicators. Turn to the side, the indicator light cycle. Brakes, lights all light
qicheweideng
- 实现汽车尾灯的各种状态的灯的转换，用以改善现在汽车尾灯的复杂程度-To achieve automotive tail lights various states of transition
Automobile-tail-light
- 汽车尾灯的设计 基于FPGA的设计 可以仿真运行-Car taillight design FPGA-based design simulation run
car_light
- 基于VHDL的汽车尾灯控制器，Quartus2,9.0-VHDL-based automotive tail lights controller, Quartus2, 9.0
Automobile-taillights
- 这是应用VHDL语言在FPGA上实现汽车尾灯的程序（源代码）-This is a car tail lights on the FPGA using VHDL language program (source code)
tail-light
- 利用vhdl语言完成车尾灯的简单控制，实现刹车，左转，右转的功能 通过测试并运行成功。-Vhdl language to complete the simple control of the taillights, brake and turn left, turn right to the function by testing and running successfully.
qicehweideng
- 汽车尾灯控制电路的设计，正常行驶时，6个尾灯全灭，刹车时，尾灯按一定频率闪烁，左转时，左侧灯轮流闪烁，右转时，右侧的灯轮流闪烁。-Control circuit design taillights, normal driving, six taillights Quanmie, brake, tail lights flashing at a certain frequency, turn left, turn left flashing lights, turn right, the righ
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
conv_encoder
- TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code