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SystemVerilog_2nd.pdf
- System Verilog 验证设计。主要讲如何编写测试用例。设计数字电路比较经典的教程。-System Verilog design verification. Mainly about how to write test cases. Digital circuit design more classic tutorial.
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Testbenching-Example
- FPGA设计测试用例介绍PPT文档，对于初写测试用例很有帮助。-FPGA Design of test cases to introduce PPT files, helpful for the beginning of writing test cases.
dianziqin
- 电子琴， 利用实验箱的脉冲源产生1，2，3，。。。共7个或14个音阶信号； 用指示灯显示节拍；能产生颤音效果。-Organ, using a pulse source generated test cases 1,2,3,. . . A total of 7 or 14 chromatic signal with the indicator shows the beat to produce vibrato effects.
static_pll
- 介绍如何使用ProASIC3/E的Static PLL，从例化到下载测试的整个过程。-Describes how to use the ProASIC3/E of the Static PLL, to download the test from the cases of the whole process.
two_port_ram
- 介绍如何使用ProASIC3/E的Two Port RAM，从例化到下载测试的整个过程。-Describes how to use the ProASIC3/E of Two Port RAM, to download the test from the cases of the whole process.
fpga-based-experiment
- fpga实验在多种情况下 用途广泛 这里有许多常用的实验 基础 简单 易上手-fpga test widely used in many cases, there are many common experimental basis for a simple approachable
Being
- 程序实现了两位数码管1分钟倒计时，实验由试验箱实现。-Procedures for the two festivals in one minute to count down. the experiment by the test cases.
myfpga
- 详细描述设计过程 ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义） ⑦ 实验总结，在调试和下载过程中遇到的问题 -Design Pr
sp6ex18
- 基于Verilog HDL的对片内RAM进行连续读写测试实例-Based on the on-chip RAM for continuous reading and writing test cases for Verilog HDL
fadder4
- 例化语句生成的四位全加器代码，写在word里了，也有MODELSIM测试代码-Four cases of full adder codes generated by the statement, written in the word again, and there MODELSIM test code
sp6_SRAM
- SRAM读写测试实例，每秒钟进行一次单字节的SRAM 读和写操作，用chipscope查看时序波形。 -SRAM read and write test cases, once per second single-byte SRAM read and write operations, with chipscope view waveforms.
AES加密算法密码模块
- 其实现了AES加密中的密码模块，包含了功能的说明，模块以及测试用例，学习上手的难度较小(The realization of the AES encryption password module, contains a descr iption of the function modules and test cases, learning difficult to get started)
FIFO_UVM
- fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving prop