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frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
clock
- Verilog 编写的60进制的计数器，可以用来设计数字钟、频率计等-count_60 for digital clock using Verilog
lab1
- 利用内部时钟实现24位计数的功能，10进制，无分频，verilog语言编写-The use of the internal clock function 24 counts, 10-band, no division, verilog language
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
shuzizhong
- 介绍了简单的数字钟，verilog语言。包括两位时钟数字和两位分钟数字和两位秒钟数字。-It introduced a simple digital clock, verilog language. Including two digital clocks and digital two minutes and two seconds digits.