搜索资源列表
i2c(FPGA)
- 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
canbus(FPGA)
- 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run
masterspiverilog
- spi总线控制器的fpga实现 verilog源代码及测试
MQdecoder
- Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA， Verilog HDL
Huffmann-Coding-FPGA
- huffman coding in vhdl or verilog with explanation
fpga-jpeg
- JPEG硬件解码器设计 verilog实现-JPEG hardware decoder design verilog implementation
MPEG2_MAC_Verilog_FPGA
- MPEG2+MAC Verilog代码+文档(FPGA实现)-MPEG2+MAC Verilog code the+ document (FPGA implementation)
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
fpga-jpeg
- jpeg编码verilo语言的FPGA实现-jpeg encode fpga implement with verilog
fpga-jpeg-Verilog
- jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
Display-a-heart-shape-code
- Display a heart shape code点阵显示爱心形的FPGA Verilog 代码-Display a heart shape code
Key-and-digital-tube-display
- 按键和数码管显示，FPGA的verilog代码-Key and digital tube display
Multiplier-digital-tube-display
- 乘法器数码管显示，FPGA的verilog代码-Multiplier digital tube display
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display
test_5.0_tetris
- 基于Vivado实验平台，用Verilog语言编写的俄罗斯方块，可以在FPGA硬件上上下载运行(Based on the Vivado platform, the Tetris block written in the Verilog language can be downloaded on the FPGA hardware.)
lzs-master
- 基于verilog的LZS压缩和解压算法，压缩比1；2 。里面带有C原言的代码。已经通过验证！(Verilog based LZS compression and decompression algorithm, compression ratio 1; 2. It has the C code in it. It has been verified!)