12-modulo counter in Verilog. Counts up and down, devides by 2, stops, resets. If <5 Y = 1 . Counter.v is behavioral, counter_b.v - gates level.-12-modulo counter in Verilog. Counts up and down, devides by 2, stops, resets. If <5 Y = 1 . Count

A classic booth multiplier implemented using verilog HDL using the Xilinx software.