搜索资源列表
Verilog编码与综合中的非阻塞性赋值CummingsSNUG2000SJ_NBA_rev1_2.rar
- Verilog编码与综合中的非阻塞性赋值
Verilog
- verilog经典书籍,绝对经典。硬件描述语言(第四版)
大量verilog代码
- 大量verilog设计实例
verilog数字时钟论文及代码
- verilog数字时钟论文及源代码
Verilog HDL的基础教程
- Verilog HDL的基础教程PDF资料
用Verilog和VHDL设计状态机的论文
- 详细介绍了用Verilog和VHDL设计状态机的技术。
teach~verilog 教学
- 將工作多年的經驗談分享給大家 希望大家在VERILOG這塊領域上會有所助益
矩阵键盘 verilog
- 用verilog写的 矩阵键盘
verilog与ISE
- verilog与ISE系列的,非常好
SPI-in-Verilog-implementation
- SPI的Verilog实现(非常的全面和详细,还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
Verilog编码与综合中的非阻塞性赋值CummingsSNUG2000S
- Verilog编码与综合中的非阻塞性赋值-Verilog code and synthesis must blocking evaluation
Verilog
- Verilog语言学习资料,希望对给为有一点帮助哈-Verilog language learning materials, hoping to have some help on to Kazakhstan
verilog-traffic-light
- 基于VerilogHDL设计的交通灯控制系统本设计利用Verilog HDL 语言、采用层次化混合输入方式,可控制4个路口的红、黄、绿、左转四盏信号灯,让其按特定的规律进行变化。 -This design using Verilog HDL language, adopt hierarchical mixed input method, four intersection control of red, yellow, green, left four lamp lights, let its
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstractio
Advanced Digital Design with the Verilog HDL
- Advanced Digital Design with the Verilog HDL (M.D.Cilett)
夏宇闻verilog数字系统设计综合教程
- 夏宇闻的经典书籍:夏宇闻verilog数字系统设计综合教程(Xia Yuwen classic books: Xia Wen Verilog digital system design tutorial)
三角函数的Verilog HDL语言实现
- 以Actel FPGA作为控制核心,通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波,利用Verilog HDL语言实现死区时间可调的SPWM全数字算法,并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, rea
Verilog的135个经典设计实例
- Verilog的135个经典设计实例,Verilog从业者学习者的很实用的资料(Classic design examples based on Verilog)
verilog分享--verilog快速掌握之模块例化
- 快速掌握verilog实例化分享程序,对于使用verilog编写的固件,需要功能划分,体现实例化的用处,便于归档提取,以备再次使用(Quickly grasp the Verilog instantiation sharing program, for the use of Verilog firmware, the need for functional division, to reflect the usefulness of instantiation, easy to archive
Verilog-数字频率计
- 实现了利用verilog在FPGA系统上实现的数字频率计,三个档位可供选择。(The digital frequency meter implemented on the FPGA system by Verilog is realized, and three files can be selected.)