搜索资源列表
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
hdb3
- 该代码使用Verilog HDL语言编写的，能够对HDB3码进行编译，该文件是完整的，可以直接在ISE软件上运行-Compile the code using Verilog HDL language, HDB3 code, the file is complete, you can run directly in the ISE software
Useful_data
- Full flow descr iption of the flow of developing the verilog code in ISE and steps in implementing and executing in fpga
Pilot_Insert
- 导频插入，此程序用ISE的verilog编写，主要用于载波提取和采样频率同步-Pilot insertion procedures prepared by the ISE verilog, mainly used for carrier extraction and sampling frequency synchronization
CooperativeCommunication
- 1. 研究空时分组码的编译码原理及算法； 2. 研究了几种不同的协作分集系统模型和协作分集协议； 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现，并在ISE集成环境中综合仿真，结果正确后下载到FPGA电路板上； 4. 用示波器观察输出数据是否正确，验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several differen
tiaopin
- 此程序用ISE的verilog编写，主要用于调频通信系统中，经过仿真，正确，希望对大家有帮助-This program was written with the ISE verilog mainly used for FM communications systems, simulation, and right, and I hope for all of us to help
AXI_MIG
- ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
key
- PS2键盘协议代码 verilog，可以在ISE上跑，约束条件：NET"F50M" LOC="B8" NET"ps2_clk" LOC="R12" NET"ps2_data" LOC="P11" NET"rst" LOC="H13" NET"seg[6]" LOC="L18" NET"seg[5]" LOC="F18" NET"seg[4]" LOC="D17" NET"seg[3]" LOC="D16" NET"seg[2]" LOC="G14"
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
Triangle
- 在ISE环境下，使用Verilog语言，编写三角波程序，运用ModelSim进行仿真。-In the ISE environment, use Verilog language, written in a triangular wave program, using ModelSim simulation.
experiment_4_uart_communication
- 这是一个uart串口通信的代码，是基于ise运行的verilog语言，可以实现上位机和开发板的通信以及开发板显示数据并返回累加和的功能。- This is a serial code for uart communication is based on running ise verilog language, you can achieve PC and development board communications, and development boards to display
verilog-ethernet-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
verilog-image-decompressor-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
verilog-uart-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
SDRAM-and-FIFO-for-DE1-SoC-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
SRAM
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.