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oaVerilog
- openaccess与verilog互相转化时所用的源代码，在安装了openaccess的windows和linux上都可以使用。-openaccess with Verilog into each other when used in the source code, the installation of the windows and openaccess on Linux can use.
rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplic
pwm_VerilogHDLV1.1
- 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
VHDL.rar
- 16QAM调制器的Verilog HDL程序，可以实现16QAM调制,16QAM modulator Verilog HDL procedures, 16QAM modulation can be achieved
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
flash02
- 一个我自己写的FPGA读写FLASH代码，在QUARTUS 下用verilog编写，falsh的型号是k9f5608u0d,经测试可以用。-I wrote a FLASH FPGA to read and write code, written in QUARTUS next with verilog, falsh model is k9f5608u0d, can be tested.
speech
- 用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
ldcp_verilog
- ldpc verilog 程序 做ldpc硬件实现的可以-ldpc verilog procedures do LDPC hardware implementation can
miaobiao
- verilog写的分频程序,可以对输入的频率分频-Verilog write the sub-frequency procedures, can the frequency of the input frequency
time_display
- 用Verilog实现的电子时钟显示器，可以显示24小时制的时间-Using Verilog implementation of the electronic clock display, can display 24-hour time
wddc_module
- 数字下变频的Verilog程序，测试可以直接使用，将A/D信号下变频为基带I，Q两路信号-Digital down conversion of the Verilog program, testing can be used directly to A/D signal down-conversion to baseband I, Q signals two
USBverilog
- verilog USB程序，经过实践调试，并且都能成功实现-verilog USB procedures, debugging practice, and can be successfully achieved
CPU_code
- 基本的cpu verilog code 可用來瞭解基本cpu運作-Basic cpu verilog code can be used to understand the operation of the basic cpu
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
VerilogExamples
- Verilog大量例程，可用于Verilog的学习-Verilog a large number of routines that can be used to learn Verilog
seg7_counter
- 這是一個提供上下數的七段顯示器之verilog的程式。透過此程式可簡易的學習如何撰寫程式來控制七段顯示器。-This is a seven-segment display to provide the upper and lower number of verilog program. Through this program can be simple to learn how to write programs to control the seven-segment display.
Verilog-Vending-Machine-_-georgeBlog_-A-blab-on-t
- using vending machine we can collect ice cream along with a change or can be fullfilled by any other subsequent cooldrinks
Examples-from-Verilog-HDL
- 国外经典verilog代码，非常适合初学者自学，同时有些概念老手也可以仔细琢磨琢磨-Foreign classic verilog code, very suitable for beginners self-study, while some of the concept of a veteran can also be carefully pondering pondering. .
UART_RS232(verilog)
- /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作
Verilog--75076ICQ76794102
- 找了这么久的源码，今天终于找到了这个源码 Verilog 75076ICQ76794102，同学们可以学习参考-Source for so long, today finally found the source Verilog- 75076 icq76794102, students can learn the reference