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ExpressAnalysis
- 表达式分析, 支持算术运算,括号,关系运算,逻辑运算,字符串的like运算等。采用了有限自动机做词法分析, 语法分析用算符优先分析方法，正负号算符使文法不是OPG，因此这里作了特殊处理。分析的结果是逆波兰式, 存在一个链表中。在逆波兰式的基础上，用一个栈来进行求值。在vc++6.0下试验通过。 如有问题，可以mail: zch888email@163.com 我将尽快回复你。-expression analysis, supports arithmetic operations, bra
j2
- 多功能运算器- Multi-purpose logic unit
lgt2330
- ogtalk是一种面向对象的逻辑编程语言，可以使用最Prolog的实现作为一个后端编译器。 -ogtalk is a logic of object-oriented programming language, you can use most Prolog realization as a back-end compiler.
lw237ese_grifo
- Ladder logic compiler for 8051 microcontroller
compiler
- 一个微型的编译器的实现代码。主要是为了说明编译器的工作原理，从中揭示编译设计的一些简单道理。编译器是一种比较复杂的程序，一般情况一个可以商用的编译器代码量都在10万行到100万行之间。所以本代码是一个相对简单的编译器模型。-A miniature of the implementation of the compiler code. Mainly in order to explain the working principle of the compiler from compiler des
GRSORT7.PAS
- Pascal program implementing a number of different array sorting methods and providing interface to test them for effectiveness in different initial data conditions. Interface is designed to be in Russian but all the other logic is internationsl. Can
clRLL17c
- Cirrus Logic RLL 1,7 encoder and decoder
ddd
- 组合逻辑的分析及应用，译码器，编码器的理解，应用-Combinational logic analysis and application, decoder, encoder, comprehension, application,
point
- 一个简单的脚本语言解释器，可以编写基本逻辑，-A simple scr ipting language interpreter, you can write the basic logic
linistepper-c
- C++ logic stepper controller
decoder3to8
- 用组合逻辑电路写的3/8译码器，非常简单，是初学者可以看看的-Written with a combination of logic circuit 3/8 decoder is very simple, a beginner can look at the
byyl
- 编译原理，实现基本的编译器，是编译原理实验。从中有源码，实现基本的算术运算，逻辑运算，以及一些基本语句。-Compiler theory, to achieve the basic compiler, compiler theory experiment. From a source, to achieve the basic arithmetic operations, logic operations, as well as some basic statements.
PLC_Compiler
- 1、该工程用于PLC梯形图与逻辑语言之间进行转换。 2、PLC命令格式与三菱的PLC指令兼容。-1, the project is used to convert between the PLC ladder logic language. 2, PLC command format is compatible with Mitsubishi PLC instructions.
tebench_seq
- this sequence circuit testbench, in logic , aginst combinational . Verilog HDL .v-this is sequence circuit testbench, in logic , aginst combinational . Verilog HDL .v
BitToBin
- 本C程序的目的是将硬件工程师测试电路板并从逻辑分析仪获取位流，将位流转换为标准Hex内容的Bin文件-The purpose of the C program is the hardware engineers to test the circuit board from the logic analyzer for bit stream, the bit stream is converted to standard Hex Bin file content