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jianpansaomiao
- 键盘模块，基于VHDL的源码，用于做计算器以及其他小型模块的应用-keyboard module, based on VHDL source code, spent calculators and other small application module
pp-1.5.7RC
- Parallel Python (PP) PP is a python module which provides mechanism for parallel execution of python code on SMP (systems with multiple processors or cores) and clusters (computers connected via network). It is light, easy to install and int
jp
- 键盘输入模块（利用按键来获取我们所需要设定的值）并将这个值进行计算-Keyboard input module
module.tar
- 此文件为Karman改进源码用来对源karman程序运行时间进行预测，文件中的karman为基于karman源程序的建模-karman modified code which is used to bulid a model to give the prediction of running time.
test
- 一个TOP模块实现并行计算，一个TOP模块实现并行计算-A TOP module parallel computing, a TOP module parallel computing
z8051
- 在libero8.1环境下，用Verilog描述的8051内核，可以包括各个基本模块，可以仿真。-In the libero8.1 environment described in Verilog 8051 core, including the basic module can be simulated.
uart
- 用verilog描述的uart收发模块，比较经典。-With the the UART transceiver module Verilog described, classic.
SX
- 基于Proasic3 startkit开发板，描述了8位地址锁存芯片74ls259和Uart接受模块，通过这两个模块来控制开发板上的led.-Based on the the ProASIC3 StartKit development board, describes the 8-bit address latch chip 74LS259 and the UART receiving module, to control development board led by these two m
SDRAM_FPGA
- 这个是SDRAM的控制程序，包括包括UART和FIFO模块，适合FPGA开发人员看，也适合初学者学习。-This is the SDRAM control procedures, including including UART and FIFO module, suitable for FPGA developers look, but also suitable for beginners to learn.
zhejixiugai
- 用于计算两个未知长度信号的褶积程序，它可以作为反滤波中的一个小模块使用-Used to calculate the two signals of unknown length convolution procedure, it can act as inverse filtering in a small module
tancishe
- 本文以msp430f169为控制核心，12864为显示模块，通过两个外部按键的控制实现他吃蛇游戏-In this paper, msp430f169 as the control center, 12,864 for the display module, via two external buttons control to achieve his eating snake game
rs_code
- CMMB 移动多媒体广播数字电视激励器（调制器） RS编码模块-CMMB mobile multimedia broadcasting digital television exciter (modulator) RS coding module
vga_controller_stream
- VGA控制模块，经过测试，简单易用-VGA control module, tested, easy to use! ! !
alu16
- 16位运算器，用实例化模块链接，是采用Verilog hdl编程，是实现fpga的代码-16-bit arithmetic unit, with links to instantiate module is using Verilog hdl programming, is to achieve the fpga code
sn74181
- 4位运算器采用sn74181，是采用Verilog hdl编程，是实现fpga的代码，实现了其模块的48种功能，-4 operator uses sn74181, is the use of Verilog hdl programming, is to achieve the fpga code, achieved its module 48 kinds of functions,
md
- 曼彻斯特编码的实现，Verilog模型。测试通过-FPGA Verilog Module.
axi_slave
- AMBA axi利用verilog搭建的axi_slave模块-AMBA axi use verilog module built axi_slave
1302
- 时钟芯片实现计时，可调，以及12864液晶显示模块程序，可根据个人需要对程序做些少改动即可达到所要的功能-Clock chip timing, adjustable, and 12864 LCD module procedures, fewer changes to the program based on individual needs to do to achieve the desired function
CRC32_II
- 基于第二类LFSR串行CRC生成器的32位并行实现结构。用于SATA 3。 verilog语言。-32bit parrallel CRC module as specified in SATA 3. The module is realized with verilog.
get_e_de
- 模糊控制器 误差生成模块.V文件及testbench文件-Fuzzy controller error generation module .V file and testbench files