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AD7864
- 这是对上次AD7864采样程序的改进，增加了FIFO的编程，功能比上次源码更加完善！-This sourse is modified and I have added the program of FIFO,so its function is better then privious one.I hope it is helpful for you!
FIFOexperience
- 华为内部关于FIFO的经验之谈，深入了解FIFO-Huawei on the FIFO' s internal experiences
program
- 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi
fifo
- 利用一个SAM设计一个FIFO 的存储器-SAM uses a design of a FIFO memory
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
clk
- 通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。-Through a master clock signal the completion of asynchronous FIFO read and write clock signal generation. Compiler through the implementation function.
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
fifodd
- 一个深度为32，字长为8_bit FIFO（先进先出）寄存器，有寄存器空、寄存器满和寄存器溢出信号。-A depth of 32, word length for 8_bit FIFO (FIFO) register, a register space, register and register full signal overflow.
UART
- A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the