搜索资源列表
FPGA
- 基于FPGA数字乘法器的设计：数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA 的数字乘法器．分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processin
cla
- Carry Look ahead adder
bitbcdadder
- bcd adder implemented in three models of vhdl
Carrylookaheadadder
- carry look ahead adder implented in 3 models of vhdl-carry look ahead adder implented in 3 models of vhdl
FOURBITRIPPLECARRYADDER
- four bit ripple carry adder implented in 3 models of vhdl-four bit ripple carry adder implented in 3 models of vhdl
5PG
- Design of High-Performance Low-Power Carry Select Adder using Dual Transition Skewed Logic (DTSL)I
Adder
- Adder Ckt..designeed using shpoice
serial-adder
- VHDL code for adding two hard-coded 8-bit binary numbers
serialadder
- serial adder in behavioural model
A-New-Reversible-Design-of-BCD-Adder
- Designing a BCD adder
21-bit--leading-adder-Verilog
- 这是一个21位超前进位加法器的verilog程序。-21 bit leading adder verilog program.
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
16-leading-adder-Verilog-program
- 这是一个16位超前进位加法器的Verilog程序。-This is a 16 bit leading adder verilog program.
Four-serial-binary-adder
- 用Quartus II软件原理图编写四位串行二进制加法器-Principle of Quartus II software, written in four serial binary adder
adder
- 简单的加法运算,让初学者了解java的加法运算过程-Simple addition operations, allow beginners to understand the process of java adder
ANALYSIS-OF-HALF-ADDER
- REGARDING HALF ADDER
DIC-adder-report
- 介绍carry skip adder以及几种实现方式，最后进行性能评估-introduction to the carry skip adder,and several ways to realizing it, and judging their performance
carry select adder in vhdl
- carry select adder in vhdl
carry skip adder vhdl
- carry skip adder vhdl
carry-select-adder
- Carry Select adder 32 bits in vhdl