搜索资源列表
phase_test
- 基于verilog的鉴相器设计，鉴相器是锁相环的一部分，功能是检测两个时钟是否同步-The phase detector based on verilog design, PLL phase detector is part of function is to test whether the two clock synchronization
pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
clock
- 多功能数字钟的Verilog ＨＤＬ源代码程序的实现-ｍｕｔｉｌ－ｆｕｎｃｔｉｏｎ ｄｉｇｉｔａｌ ｃｌｏｃｋ Verilog ＨＤＬ
shuzishizhong-verilog
- 基于2410开发板数字时钟的开发，实现了计时，日期，跑表的功能-Based on the development of the 2410 development board digital clock, a time, date, stopwatch function
digital-Timer
- 数字时钟，使用Verilog实现，已经调试过了-Digital clock, using Verilog implementation
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
shixunlaozhong
- 基于Verilog HDL语言的多功能数字钟，能够实现置位和清零功能。 -Verilog HDL language-based multi-function digital clock, to achieve set and clear functions.
data_clock
- 基于verilog 的数字钟设计过程，含有详细的代码和解释。-Based on the design process verilog digital clock contains a detailed code and explanation.
clock
- 这是紫外光通信PPM调制设计系统中的时钟信号设置。用Verilog语言编辑并且编译成功，希望对大家有帮助-This is the clock signal in the PPM modulation design of ultraviolet communication system Settings. Edit and compile successfully with Verilog language, hope to help everyone
Verilog-Code-For-Digital-Clock-Project
- Verilog code for digital clock project
VHDL100
- 本文件包含100个Verilog实例，有存储器，时钟，椭圆滤波器，状态机等。有助于初学者的学习。-This document contains 100 examples of Verilog, there are memory, clock, elliptic filter, state machines. Help beginners to learn.
shizhong
- 基于Verilog HDL语言的数字时钟程序，有秒脉冲，，计数，译码显示等部分-based on Verilog HDL language,about clock