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loongson
- 龙芯2E处理器用户手册 中国科学院计算技术研究所 意法半导体公司 2006年 9 月 龙芯2E处理器是一款实现64位MIPS III 指令集的通用RISC处理器。龙芯2E的指 令流水线每个时钟周期取四条指令进行译码，并且动态地发射到五个全流水的功能部件 中。虽然指令在保证依赖关系的前提下进行乱序执行，但是指令的提交还是按照程序原 来的顺序，以保证精确中断和访存顺序执行。 -Godson 2E processor user manual CAS Institute of Comp
~CDDBNY834200PDF
- 探讨RISC32处理器设计中三个关键问题包括多媒体指令集扩展设计、流水线微结构优化设计以及使RISC32成为一个真正IP核的其他相关设计问题-explore RISC32 processor design three key issues, including the expansion of multimedia instruction set design, pipelined micro-structural optimization design and make RISC32 beco
pipeline_10b_adc
- 10bit pipelined adc in matlab
platforms
- A Pipelined Implementation of AES for Altera FPGA platforms.doc
TheResearchoftherealtimesignalprocessingofSARbased
- 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging ar
pipeline_3bADC
- 3bit pipelined ADC in matlab
pipeline_6bADC
- 6bit pipelined adc in matlab
222
- pipelined multiplier accumulator architecture
VLSI_Architectures
- 超大规模集成电路算法和流水线架构设计，高级IC进阶-VLSI algorithms and pipelined architecture design, advanced IC Advanced
ASE
- 可重构平台下AES算法的流水线性能优化，讲解比较到位，抛砖引玉可以-Reconfigurable platform performance optimization of pipelined AES algorithm, to explain more in place, so you can
256MbSDRAMx32
- • PC100 functionality • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/pr
shruthi-proj
- The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high
An-Adaptively-Pipelined
- 数字滤波器，FIR,IIR，大容量管道，数字滤波器芯片，英文文献介绍-filter chips
new-k-best-dection
- 研究MIMO系统检测算法理论及其实现方法的基础上，对已证明较优的算法进行结合和改进，提出了一种改进的K—Best检测算法及其实现方案，并通过仿真验证了方案的可行性。该算法采用预测技术和并行排序相结合的方法，降低了计算复杂度；采用并行流水线结构实现，节省了处理时-Basic research MIMO system detection algorithm theory and its implementation methods, have proven to be the optimum com
improve-k-best
- 研究MIMO系统检测算法理论及其实现方法的基础上，对已证明较优的算法进行结合和改进，提出了一种改进的K—Best检测算法及其实现方案，并通过仿真验证了方案的可行性。该算法采用预测技术和并行排序相结合的方法，降低了计算复杂度；采用并行流水线结构实现，节省了处理时间；并对方案在xilinx公司的Virtex_5系列n)GA中的资源使用情况进行了统计。研究表明，实现方案可以用于MIMO系统检测算法的硬件实现。-Basic research MIMO system detection algorithm
FPGA-DESIGN-OF-A-HARDWARE-EFFICIENT-PIPELINED-FFT
- The digital wideband receiver is a critical component in modern digital receivers. The receiver has the capability to expose and distinguish adverse signals contained within a large bandwidth (on the order of 1 GHz or more) of the radio frequency (RF
A-Fast-CRC-Implementation-on-FPGA
- 快速实现crc polynom fpga使用流水线架构-A Fast CRC Implementation on FPGA Using a Pipelined Architecture for the Polynomial Division
pipelined-mips-cpu-master
- misp 5 stage pipeline
06118316
- Pipelined Radix- Feedforward FFT Architectures
184081165-16-Bit-Wave-Pipelined-Sparse-Tree-RSFQ-
- In this system, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2ADP2.1 fabrication process. Compar