搜索资源列表
m16550a_verilog_rtl
- mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
SPI-in-Verilog-implementation
- SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
UART_spec
- a UART model with FIFO buffer, design with verilog
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
lab3
- verilog source code for uart design
uart
- UART schematic and code
xapp341
- verilog uart for spartan 3 fpga, its great
FPGA--uart(verilog)
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
FPGA---buld-gennerate
- verilog uart 源码，编译器ISE9.1i版本，很有用的源码-verilog uart code
chapter9
- 一个别人写的ＵＡＲＴ ｖｅｒｉｌｏｇ程序，希望对大家有帮助-A UART verilog program written by someone else, we want to help
UART
- design IP UART by Verilog, VHDL-design IP UART by Verilog, VHDL...
UART
- 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
verilog-uart
- UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
18.uart
- 用Verilog HDL编写的uart程序，亲测可行，注释很详细！-Written using Verilog HDL uart program, pro-test is feasible, very detailed notes!
uart
- 基于Verilog HDL设计的UART
rs232_des
- uart verilog code using ram and a-uart verilog code using ram and all
uart
- RS232接口，uart用verilog语言实现-RS232 interface, uart with verilog language
uart
- 该模块是基于串口协议用verilog实现了串口的接收和发送功能。-The module is based on a serial port protocol using verilog to realize the function of receiving and sending of the serial port.
黑金Sparten6开发板Verilog教程V1.6
- 黑金spartan的开发板教程，包含了各类接口如spi，uart，vga的用例，以及各项存储器如flash，ddr的操作方法(spartan 6 example design)
verilog编写uart验证有效版.rar
- verilog编写uart验证有效版.rar