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pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
shuzishizhong-verilog
- 基于2410开发板数字时钟的开发，实现了计时，日期，跑表的功能-Based on the development of the 2410 development board digital clock, a time, date, stopwatch function
digital-Timer
- 数字时钟，使用Verilog实现，已经调试过了-Digital clock, using Verilog implementation
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
data_clock
- 基于verilog 的数字钟设计过程，含有详细的代码和解释。-Based on the design process verilog digital clock contains a detailed code and explanation.
clock
- 这是紫外光通信PPM调制设计系统中的时钟信号设置。用Verilog语言编辑并且编译成功，希望对大家有帮助-This is the clock signal in the PPM modulation design of ultraviolet communication system Settings. Edit and compile successfully with Verilog language, hope to help everyone
Verilog-Code-For-Digital-Clock-Project
- Verilog code for digital clock project