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origen_s5pv310_eva_cpuboard Samsung S5PV310 Exynos 4210处理器
- Samsung S5PV310 Exynos 4210处理器,CORTEX A9 双核，支持DDR3-Samsung S5PV310 Exynos 4210 processor, CORTEX A9 dual-core, support for DDR3
DDR_Eye_Patterns
- DDR1 DDR2 DDR3眼图分析。本文根据自己设计的DDR“读”“写”分离软件，介绍一种把“读”眼图和“写”眼 图分离开的方法，并创新地引入模板测试的方法。-DDR1 DDR2 DDR3 Eye Patterns
ASP_7738G_DDR3
- Schematic Diagram for Acer Aspire 7738G DDR3 Laptop.
sdram_introduce
- sdram内存技术指南（sdr,ddr,ddr2,ddr3）-sdram memory technology guide (sdr, ddr, ddr2, ddr3)
JESD79-3E
- This document provides implementation instructions for the DDR3 interface-This document defines the DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this
xapp741
- xilinx视频处理包示例，包括VDMA，VTC，DDR3控制等。-Xilinx video processing package example, including VDMA VTC, DDR3 control, and so on.
ddr
- davinci平台dm8168外接DDR3功能测试-davinci dm8168 external DDR3 functional test platform
The-difference-between-DDR3-andDDR2
- 这个文档详细描述了DDR3与DDR2之间的区别所在-this doc tells details the differences between DDR3 and DDR2
1
- 。针对高速实 时数字信号处理中大容量采样数据 通过DDR3 存储和读取的应用背景，-java linux
DDR3
- 。针对高速实 时数字信号处理中大容量采样数据 通过DDR3 存储和读取的应用背景，-DDR3 FPGA
RK306-SDK-DDR3
- SDK for Rockchip RK30-SDK for Rockchip RK3066
DDR3-SDRAM-controller
- My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.
DDR3
- this about ddr3 document and a good file to be refered -this is about ddr3 document and a good file to be refered
Zynq-Mini-ITX-Rev-E
- Zynq Mini-ITX 单芯片可编程SOC(ARM+FPGA)开发板电路原理图 -Zynq Mini-ITX Development Board Schematics the Zynq Mini-ITX development board features 2 GB DDR3 SDRAM, PCIe Gen2 x16 Root Complex slot (x4 electrical), SATA-III interface, SFP interface, QSPI Flash me
xilinx-DDR3-sdram-design
- xilinx平台DDR3设计教程之设计篇 -XILINX DDR3 SDRAM DESIGN
R8M_DataSheet_V02
- This document describes the application information of R8M Module that includes Allwinner Tech’s high performance processer R8 and 64Gb NAND Flash/4Gb DDR3 memory MCP. R8M is highly integrated, low power consumption, lower system cost module, which i
A13-Brief
- This document describes the application information of R8M Module that includes Allwinner Tech’s high performance processer R8 and 64Gb NAND Flash/4Gb DDR3 memory MCP. R8M is highly integrated, low power consumption, lower system cost module, which i
DDR3_ip
- 本文档开发环境为vivado软件，描述了ddr3 IP core的生成过程，亲测可行。-this document describe ddr3 ip core genetator process.I test it by myself.
XILINX_DDR3_IP核使用教程
- 详细介绍了Xilinx DDR3 IP核的使用方法和注意事项(The usage and attention of Xilinx DDR3 IP core are introduced in detai)
DDR3读写测试
- MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)