搜索资源列表
DDR3
- DDR3控制器，基于Altera平台，修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
ddr3_mcib_rmbs
- DDR3走先得详细规则及注意事项，考虑的等长走线，数据线与地址线、控制线长度关系-DDR3 take detailed rules and precautions come to consider the alignment of equal length, the data line and address lines, control lines the length of the relationship between
MT41J64M16LA-187E
- Micron DDR3 内存 MT41J64M16LA-187E schlib.-Micron DDR3 MT41J64M16LA-187E symbol lib .
software
- ddr3 Test program for Altera FPGA Starter Kit
52K_19200_1_2010.02.08.16.06.44_4247_KO[1].pdf.zi
- DDR3 SDRAM datasheet please refer want to development DDR3 Controller
94117c05d50c
- Its a clock Sequence for DDR3 Controller.Hope u find it useful
ddr3_controller1
- ddr3 controller for axi interface
1G-NANDP1G-DDR3-(Rev_01)
- 1G Bit (129Mx8) Nand flash / 1G Bit (8Mx16x8Banks) DDR3 SDRAM
DDR3-SDRAM-Verilog-Model(1)
- contains the information and codes of DDR3 memory model
DDR3-SDRAM-Standard.pdf
- DDR3 Standard document,内存规格书，参考，详细-DDR3 STANDARD DOCUMENT
DDR3-SDRAM-Controller
- DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
ddr3
- VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.
DDR3-SDRAM-Verilog-Model
- ddr3模型以及代码和测试程序，不过带有小瑕疵-ddr3 model and code and test procedures, but with small flaws
Lattice-DDR3
- littice ddr3的仿真教程，主要讲解怎么仿真littce 的ddr3，和littice ddr3的基本知识的讲解-explain the basics of lattice ddr3 simulation tutorial, mainly on how simulation little of ddr3, and littice ddr3 of
DDR3 SDRAM Verilog Model
- ddr3的逻辑带么参考，有需要的可以看一下。。。。。。。。。(ddr3 ssscoede code code code)
ddr3
- FPGA实现DDR3控制器()
DDR3
- spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)
DDR3的工作原理
- DDR3原理，详细的介绍了DDR3内部结构以及工作原理(DDR3 principle, detailed introduction of the internal structure of DDR3 and the principle of work)
XILINX平台DDR3设计教程
- 从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)
ddr3
- ALINX7010 ddr3读写测试仿真实验官方教程 附说明和代码 Vivado 实现(Alinx7010 DDR3 read write test simulation experiment official course Descr iption and code attached Vivado implementation)