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VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
Verilog
- 是摩托罗拉关于Verilog HDL的开发规范，相信对于学习Verilog程序设计的人会有很大的帮助-Motorola on the development of Verilog HDL specification, I believe that learning Verilog for programming will be of great help to people
fre_ctrl
- 利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL descr iption of the behavior and structure of a descr iption of the realization of frequency
verilog
- 讲述的是verilog HDL 的一些实际应用与联系。还宝库奥一些总结性的知识。-About the verilog HDL and contact some of the practical application. Treasure-house of Austria is also a number of conclusive knowledge.
i2c.tar
- i2c core for verilog hdl
i2c_customer_pack
- i2c core for verilog hdl
VerilogHDL_tuxiang
- 介绍一种用于卫星姿态测量的CMOS图像敏感器--STAR250的时序驱动信号，并使用Verilog HDL语言设计驱动时序电路。经布线、仿真、测试后验证了驱动信号的正确性。 -Introduce a measurement for the satellite attitude CMOS image sensor- STAR250 timing drive signals, and use the Verilog HDL language design-driven sequential circ
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
fft_fpga
- FFT（快速傅里叶变化）蝶形算法 Verilog HDL语言-FFT Verilog HDL
verilog-traffic-light
- 基于VerilogHDL设计的交通灯控制系统本设计利用Verilog HDL 语言、采用层次化混合输入方式,可控制4个路口的红、黄、绿、左转四盏信号灯,让其按特定的规律进行变化。 -This design using Verilog HDL language, adopt hierarchical mixed input method, four intersection control of red, yellow, green, left four lamp lights, let its
A-Verilog-HDL-Test-Bench-Primer
- 学习资料：详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed descr iption of how to use Verilog language Testbench file
verilog-hdl
- 王金明：《Verilog HDL 程序设计教程》，包括Verilog HDL的程序，对于初学者有一定的帮助-Wang Jinming: Verilog HDL programming tutorial, including Verilog HDL program, help for beginners
Verilog-HDL
- 重点介绍verilog VHL语言结构及使用方法-Highlights verilog VHL language structure and use
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
verilog-uart
- UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
Advanced-Digital-Design-with-the-Verilog-HDL-1st-
- Advanced Digital Design with the Verilog HDL 1st Ed. solution manual by Ciletti
Freescale-Verilog-HDL-Coding
- 飞思卡尔verilog语言编程规范文件,很有借鉴意义-Freescale verilog programming language specification file，Great reference
verilog-ieee
- The Verilog ¤ Hardware Descr iption Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it
verilog-hdl(VIA-COMPANY-DOCUMENTS)
- verilog hdl学习 威盛内部资料-verilog hdl language(VIA reference document)
Verilog--exzampie
- Verilog的大量代码，拿去好好学习吧-verilog hdl exzamples