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PHY_MDIO
- 光纤模块实现点对点通信,千兆网传输,基于FPGA,采用Verilog语言进行编程,实现千兆网模块的高速传输-Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module
UDP
- 利用verilog语言写的基于千兆网卡的UDP协议驱动-Use verilog language written based Gigabit Ethernet UDP protocol driver
14_ethernet_test
- 千兆网学习代码 ISE,状态机实现数据打包,基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
eth_Management_interface
- 千兆网的FPGA代码,非常有用的,请大家阅读(ethernet verilog coding,please read it and download it)