搜索资源列表
CLOCK_co-design_of_C_and_Verilog
- A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
Find_medium_value_co-design_of_C_and_Verilog
- A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
RGB_color_transform_gray_level_co-design_of_C_and_
- to use verilog code and c to translate a RGB bmp image(512*512) to a gray level image
Verilog数字系统设计教程(第2版)
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed o
DDS
- DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
MIT_Video-Scaler
- MIT的video scaler论文，文章后面附有c和verilog程序源代码，分为水平缩放和垂直缩放-MIT video scaler papers, articles, source code attached to the back, divided into horizontal scaling and vertical scaling
source3-6
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6
source11-12
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
aa
- BFGS算法本程序适用于求解形如f(x)=1/2*x Ax+bx+c二次函数的稳定点-BFGS algorithm for solving This procedure applies to the form f (x) = 1/2* x Ax+ Bx+ C quadratic function of the stable point
EchoClear
- vc++源码，消除回声处理， 可用于音频处理； -vc++ source code, deal with the elimination of echo can be used for audio processing
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
BasicRSA_latest.tar
- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman i
sha
- 内带3个sha1的C源码。经验证都可用。在我们项目中，已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
StopWatch
- 用C#写的跑表，用于学习Timer控件和C#下的stopwatch类，在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
spasion_flash_verilog_model
- verilog模型,用于仿真flash，可以快速地看懂-verilog model for flash controller specified for spasion flash, please download it look at it
ECC
- 我整理的ECC加密算法，源码和C实现的理论指导，有这个可以做出ECC加密算法-I am finishing ECC encryption algorithm, source and C to achieve the theoretical guidance, it can make ECC encryption algorithm
sc2v_latest.tar
- system C to verilog converter
Jpeg_decoder
- It is jpeg_decoder program. Source code are C and Verilog HDL.File .c reads data from jpeg and convert it to binary bit stream.Decoder is by verilog file
5-HandelC
- Handel-C语言的学习文档。Handel-C语言由C/C++演化而来，可以自动实现C到VHDL、C到Verilog、C到EDIF等转换。在DK环境中，DK+Handel-C工具能直接把基于C语言的设计转变为优化的HDL(可以实现：C到VHDL、C到Verilog、C到EDIF等的自动生成)， 进而通过FPGA实现，从而保证了各种复杂的高难算法在工程应用的实时性。(Handel-C language documentation. Handel-C language by C/C++ Evolv
Verilog codes
- IT IS A CARRY S ELECT ADDER TO IMPROVE PERFORMANCE.