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个人编写的关于积梳状滤波器的程序,用于抽取和插值时防止信号失真.-individuals prepared on the plot comb filter procedures for taking and the interpolation to prevent signal distortion.
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一个3阶的CIC内插滤波器，可作为delta sigma DAC升采样率模块，用于半带滤波器后。-a three bands CIC interpolation filter, as delta sigma DAC sampling rate or module for the half-band filter.
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用matlab设计一个抽取率为2的CIC抽取滤波器和插值率为2的插值滤波器,Using matlab to design a decimation rate of 2 of the CIC decimation filter and interpolation rate of 2 of the interpolation filter
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CIC滤波器的补偿，适用于抽取内插滤波器的设计，写昂对大家有用-CIC compensation filter, applied to extract the design of interpolation filters, write Aung useful for everyone
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利用matla设计的CIC内插滤波器，其中包含了其相应的补偿滤波器。-Matla designed using CIC interpolation filters, which contains the corresponding compensation filter.
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4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
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3级CIC抽取,内插滤波，r为抽取因子，n为原始信号的采样点数，x为原始信号序列 y为抽取滤波后的输出序列-3 CIC decimation, interpolation filter, r for the extraction factor, n the sampling points for the original signal, x is the original signal sequence y to extract the filtered output sequence
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实现了2级cic滤波器的功能，其中内插32倍，即实现了32倍的2级cic内插滤波器-Realize the level 2 cic filter function, including 32 times interpolation i.e. the 32 times the level 2 cic interpolation filter
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DVBS中可变插值率CIC滤波器设计及其FPGA实现-DVBS variable interpolation rate in the CIC filter design and FPGA implementation
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cic 滤波器，vhdl代码 ，内插与抽取-cic filter ，vhdl code about decination and interpolation
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CIC补偿滤波器设计源代码，包含量化功能，可以作为FPGA开发滤波器设计数据。适用于CIC抽取和CIC插值滤波器的补偿滤波器应用。-CIC compensation filter design source code, including the quantization function can be used as a the FPGA development filter design data. Apply to CIC decimation filter compensation an
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基于fpga的插值CIC滤波器设计,采用verilog编写，24倍插值,仿真通过-Fpga-based interpolation CIC filter design using verilog write, 24x interpolation, through simulation
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采用多级级联方法降低了对硬件运算速度的要求，有利于实时处理；采用余弦滤波器改善了阻带衰减不足；内插二阶多项式滤波器补偿了 CIC 滤波器通带内的衰减；抗混叠低通滤波器减小了混叠影响-Using multi-stage cascade approach reduces hardware requirements for computing speed, real-time processing in favor cosine filter improves the stop-band atten
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在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co
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多级插值CIC滤波器，3级、过采样率为2的8位CIC插值滤波器，系统工作时钟的频率是数据速率的2倍
-Multi-stage interpolation CIC filter 3, an oversampling ratio of eight CIC interpolating filter, the operation clock frequency of the system 2 is twice the data rate
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MATLAB CIC插值滤波器的设计方案，比较了不同插值和绘制图形插值-MATLAB CIC interpolation filter design program, compared different interpolation and draw graphics interpolated
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CIC interpolation filter which DOESNT WORK-CIC interpolation filter which DOESNT WORK!!
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抽取:(接收端)
中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。
插值:(发送端)
基带信号上变频到1M，采样率是2.5M，采用CIC滤波器进行升采样率处理。
注释：升采样率或者降采样率不会改变原始信号的中心频率，但是频谱分布会发生改变。-Extraction: (receiver)
IF signal 20M (sampling rate is 50M) down-conversion signal M
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