搜索资源列表
tx
- 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。
UART_spec
- a UART model with FIFO buffer, design with verilog
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
UART_FIFO
- Verilog 语言描述，基于FIFO设计的UART。Quartus 10中编译通过-Verilog language descr iption, based on the design of the UART FIFO
FIFOED_UART
- CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
uart
- 关于串口发送的verilog代码，实验中经常用到，已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
fifo_uart
- 使用fifo完成的串口通信。verilog语言。-fifo-uart verilog
5-verilog-programs
- the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider
sram_fifo_uart
- 用verilog HDL编写的SRAM+FIFO+UART模块，欢迎各位指点 -Welcome to the guidance written in verilog HDL SRAM+FIFO+UART module
fifo_uart
- uart的verilog代码,包含fifo，并且采用过采样以防止噪声的干扰-uart verilog code
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
uart_fifo
- 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
New_UART_verilog
- 这个是最新的UART的verilog代码，里边含有和UART相关的所有function,比如状态机，接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
uartfifo
- fifo模式下的uart串口verilog的源程序-fifo mode serial uart verilog source
uart_fifo_transceiver_verilog
- verilog UART FIFO 自发自收 自己验证过 基于EP1C3T开发板的-Verilog UART FIFO internal loopback； tested； based on EP1C3T
parameter_uart_rx
- 串口接收模块，可以通过parameter，参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数，并根据缓冲的大小配置FIFO就可以使用。对帧错误（停止位不为高），检验错误和读FIFO超时（FIFO满的情况下，有新的数据到）等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data wi
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
uart_fifo_n
- verilog 带fifo的串口收发模块(verilog uart with fifo)