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mp3
- The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, a
generic_fifos
- Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.
sc16is752
- sc16is752 device s firmware source code SC16IS752 is Dual UART with I2C/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
4432_DKDBx_(TXRX_Switch_470M)(1)
- GT033-TRX 是一款低成本的ISM 频段FSK 收发模块, 可工作在240--930MHZ 中任意频点。功率可以最大配 置为20dBm（si4432）,13dBm(si4431),接收灵敏度可达-118dBm,64 字节 TX/RX FIFOS,内置温度传感器， 8 位模数转换器,3 个I/O。支持跳频工作模式。可提供一个SPI 接口，通过MCU 设置就可调整各种参数（发 射功率.中心频点.带宽等）。无需外加功放电路就可实现远距离无线数据传输.-GT033-TRX is a l
fifos
- 通用的ｆｉｆｏ设计，带有ｔｅｓｔｂｅｎｃｈ，和ｄｅｓｉｇｎ＿ｆｌｏｗ-Fifo generic design, with a testbench, and design_flow
simple_spi.tar
- Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt gene
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
asycnFIFO
- This paper will discuss the design of an asynchronous FIFO,Asynchronous FIFOs are widely used in the computer networking industry to receive data at a particular frequency and transmit them at another frequency. An asynchronous FIFO has two diffe
UART
- A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the
fifo
- 一个先进先出的内存，使用一个同步时钟产生各种不同尺寸的高速缓冲-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
Fifo
- Shows how to set up a FIFO data queue for sharing data between real-time tasks and user-level applications. The RT task creates two FIFOs, one for commands in from the user process and one for status back to the user process. As declared in
gassplus2
- Describes the component that generates the signals required to control the data acquisition procedure consisting of: waiting for the peaking time, reading the Gassiplexes, providing the signals to the AD and writing the digitized data into the Cypres
Async_fifo_Vijay_A._Nebhrajani
- Asynchronous FIFO Architectures - Designing a FIFO is one of the most common problems an ASIC designer comes across. This series of articles (by a popular author)is aimed at looking at how FIFOs may be designed -- a task that is not as simple as
PC16550D
- PC 16550D Universal Asynchronous Receiver/Transmitter（UART） with FIFOs模块资料，串口硬件或软件人员可以参考-PC 16550D Universal Asynchronous Receiver/Transmitter (UART) with FIFOs, serial port hardware or software can refer to
FT2232H_USB_Core
- 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieve
SC16C752B
- The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission
FIFOMXN
- 该VHDL描述的是一个简单的先进先出存储器-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
HighSpeedFIFOsInSpartan-IIFPGAs
- This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be chan
generic_fifo_yh
- Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)