搜索资源列表
MICO8_DEMO_03_18_08.ZIP
- Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。,Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to supp
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
ARMcore
- 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
video_from_opencore
- 全电视信号编码器，verilog的，看看有借鉴价值否？-video signal encoder, Verilog, to see whether the reference value?
I2CSLAVE
- 已经验证过的I2C，slave的IP，core，从一开源网站下载的，代码写的非常好，节省了FPGA的资源，比起以往的slave的CORE，这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, t
uart16550_latest[1].tar
- 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
sdcard_mass_storage_controller_latest.tar
- 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
DE2_Video_SOPC_Builder_Demos
- FPGA与SOPC相结合，开成发视频播放的软ip核，可以直接使用-The combination of FPGA and SOPC, open into the hair soft ip video core, can be used directly
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
FPGA-Communication-Framework-.tar
- 这是来自开源网站OpenCores的程序，版权归作者所有，仅供学习交流。一个上位机软件源程序，和一个FPGA硬件核的源程序（<600slices），上位机软件可以通过UDP/IP连通FPGA实现通信。-This is from the open source the website OpenCores the program belongs to the author, only learning exchanges. A host computer software source cod
FPGA_website
- FPGA开发相关的国内外经典网站，有许多值得参考的设计和开源的IP核-FPGA development at home and abroad classic website, there is much reference design and open source IP core
sdram_16bit_latest.tar
- 这个IP核是一个小型的，简单的SDRAM控制器，用于为16位SDRAM芯片提供32位流水线的二叉树接口。 当访问开放行时，读写可以流水线实现完整的SDRAM总线利用率，但是读写之间的切换需要几个周期。(This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip. When acce