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leon3-clock-gate
- Clock gating logic for LEON3 processor.
ST7787
- ST7787 芯片的SPEC，比亚迪2.4inchLCM的SPEC。The ST7787 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 720 source line and 320 gate line driving circuits. This chip is capable of connecting directly to an external micr
Clock_Gating
- 本文重点详细讲述了gate clock的用法和设计-In this paper, the focus of a detailed account of the gate clock usage and design
net_test
- 程序测试成功，让程序全速运行起来后，设置板子的ip地址为192.168.2.200 主机的ip地址为192.168.2.103 程序运行开始如下： ******************************************* * * * BP2008 BIOSV1.0 * * SOFTRON BEIJING INC. * * * ******************************************* Machine Number i
HW3_P1
- Clock Controller There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CL
Intel_8086_datasheet
- Intel_8086_手册.pdf The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin CERDIP or plastic
pinlvchengxu
- ATMEGA8单片机频率计程序。原理上采用32.768K外部晶振产生异步时钟信号 ，作为M8定时器2de时钟源，设定1024de预分频，可以得到TCNT2溢出de精确时间为1s，在溢出中断时控制74ls00与非门进而控制被测信号de通断，累计1s 内计数器获得de值，经过简单de运算则可获得被测信号de频率-ATMEGA8 MCU frequency meter program. Principle produced by 32.768K asynchronous external crysta
frequency_timerA
- 基于timerA，采用计数法完成数字信号频率测量，使用片内时钟DCO时钟频率为默认值，获得金近似1s的时间闸门，即调整delay循环次数实现-Based on timerA, USES the count method is used to complete the digital signal frequency measurements, use the clock DCO within the clock frequency for default, obtain approximate
exp12
- 本实验要完成的任务就是设计一个频率计，系统时钟选择核心板上的50MHz的时钟，闸门时间为1s（通过对系统时钟进行分频得到），在闸门为高电平期间，对输入的频率进行计数，当闸门变低的时候，记录当前的频率值，并将频率计数器清零，频率的显示每过2秒刷新一次。被测频率通过一个拨动开关来选择是使用系统中的数字时钟源模块的时钟信号还是从外部通过系统的输入输出模块的输入端输入一个数字信号进行频率测量。当拨动开关为高电平时，测量系统数字时钟信号模块的数字信号，否则测量从外部输入的数字信号。-To complete
VHDL_book1
- gate：基本逻辑门的实现和验证 mux4_1_gate：多路复用器的门级实现和验证 mux4_1_behav：多路复用器的行为级实现和验证 seg7_gate：7段数码管逻辑门实现和验证 seg7_behav：7段数码管case语句描述和验证 mux7seg：采用按键复用7段数码管的实现和验证 clkseg7：采用时钟自动扫描复用7段数码管的实现和验证 comp4_gate：4位比较器结构化实现和验证 comp8_behav：8位比较器行为实现
clk-gate
- Gated clock implementation for Linux v2.13.6.
clk-fixed-factor
- basic fixed multiplier and divider clock that cannot gate.
clk-factors
- basic adjustable factor-based clock that cannot gate.
clk-gate
- Gated clock implementation for Linux v2.13.6.
clk-gate2
- basic gatable clock which can gate and ungate it s ouput.
mcrfs
- Gate off cpu clock in WFI for power saving.
clk-periph-gate
- Macros to assist peripheral gate clock for Linux v2.13.6.
gate
- OMAP gate clock support for Linux v2.13.6.
clk-gate
- Some clocks will have mutiple bits to enable the clocks, and the bits to disable the clock is not same as enabling bits.
gate
- OMAP gate clock support.omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering HSDivider PWRDN problem Implements Errata ID: i556. -OMAP gate clock support.omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering HSDivi