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dsptest
- 包括三个程序（数字信号处理器54系列试验程序加法、定时器、时钟发生器初始化）及其相关链接程序和中断向量表，已调试过，通过编译。-including three procedures (digital signal processor 54 Adder series of testing procedures, timers, clock Generator initialization) and its related procedures and links to scale disrupti
44b0_Adc
- S3C44B0X 具有 8 路模拟信号输入的 10 位模/数转换器（ADC），它是一个逐次逼近型 的 ADC，内部结构中包括模拟输入多路复用器，自动调零比较器，时钟产生器，10 位逐次 逼近寄存器（SAR），输出寄存器如下图所示。这个 ADC 还提供可编程选择的睡眠模式， 以节省功耗。 -S3C44B0X with eight analog signal input to the 10 analog / digital converter (ADC), It is a succe
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
sheji2
- 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
clk_en_gen
- 可靠的时钟产生器，采用同步设计，经过编译仿真，结果正确-Reliable clock generator, using synchronous design, compiled simulation, the results of the correct
Clock_generator
- Verilog source code for a clock generator
clock_generator
- clock generator verilog代码，供大家参考-clock generator verilog code for your reference
vhdl_code_files
- contains some self generated vhdl files. it includes a clock generator, CRc generator, pulse generator etc.
clock
- 时钟发生器，利用系统时钟获得需要的时钟信号-Clock generator, using the system clock to obtain the required clock signals
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
clock-generator-based-on-TND8688
- 基于TND86/88教学系统。设计的电子时钟。 设计思路：电子时钟主要由显示模块、对时模块和时钟运算模块三大部分组成。其中对时模块和时钟运算模块要对时、分、秒的数值进行操作，并且秒计算到60时，要自己清零并向分进1；分计算到60时，要自己清零并向时进1；时计算到24时，要清零。-clock generator based on TND8688
clock-gennerater
- NEC单片机78K0R clock generator例程，PM+开发环境系统文件及C和ASM源程序-78K0R clock generator sample program
clock-divider
- clock generator vhdl code
clock-generator
- 在集成电路设计中，时钟乃必备元素，但时钟产生器一般为模拟或者数模混合电路，在以数字电路为主的ASIC设计中，一般使用其模型来仿真。 写一个时钟产生器模块。-In integrated circuit design, the clock is an essential element, but the clock generator is generally analog or mixed analog-digital circuits, digital circuits based ASIC
Clock-Generator-for-Cavium-Processors
- Clock Generator for Cavium Processors ICS8413S09I data sheet
Clock-Generator-ad9516
- Clock Generator ad9516
clock
- Clock generator code in Verilog for Stop Watch
Application-19-Real-Time-Clock
- DSP编程，功能位实现一个实时的时钟发生器，开发软件为德州仪器的CCS-CCS DSP programming, functional position to implement a real-time clock generator, to develop software for the Texas Instruments
Clock-generator
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置-.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings
Clock generator
- A clock Generator in verilog