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cpu(FinalWithYS)
- verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
division_cordic
- verilog code for division based on cordic algorithm
TestBench
- 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_log
rsa
- 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
division
- Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB-Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB
fpu_div
- verilog code floating point division
verilog-Division-calculation
- verilog Division calculation verilog 除法计算方法-verilog Division calculation
verilog
- 這是一個除法器演算法，是利用移位的方式進行除法運算-This is a divider algorithm is the use of division shift the way
Odd-number-frequency-division
- 在FPGA中对系统时钟进行奇数分频程序，可适当改变参数对其进行任意奇数分频 verilog HDL语言-Odd number frequency division program based on FPGA
division-verilog
- 文章详解介绍了用Verilog HDL语言编写任意倍偶数分频和奇数分频的原理以及源程序，都通过仿真，结果完全正确。-The article introduced with sep Verilog HDL language writing any times frequency and the odd points even points of the principle and the frequency source program, through the simulation, the r
verilog-codes
- bit segmentation in wide division code multiple ace-bit segmentation in wide division code multiple acess
Division
- Verilog hdl 除法综合仿真实现，另包含测试文件-Verilog hdl Division
verilog-HDL-Divider
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-Division, the result (integer quotient of two 3-bit binary number) output to the digital display
division
- dvision algorithm with verilog
DIVISION
- 用verilog HDL语言编写的实现两个数相除的例程，在DE-70开发板上实现。-Verilog HDL language routines divide two numbers in the DE-70 development board to achieve.
lab1
- 利用内部时钟实现24位计数的功能，10进制，无分频，verilog语言编写-The use of the internal clock function 24 counts, 10-band, no division, verilog language
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display
division
- verilog code for division algorithm
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
verilog分享--verilog快速掌握之模块例化
- 快速掌握verilog实例化分享程序，对于使用verilog编写的固件，需要功能划分，体现实例化的用处，便于归档提取，以备再次使用(Quickly grasp the Verilog instantiation sharing program, for the use of Verilog firmware, the need for functional division, to reflect the usefulness of instantiation, easy to archive