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目前以太网PHY芯片是通过总线MDC/MDIO
- 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA
80211b-simlink.rar
- 802.11b simulink simulation source code for PHY layer. It can be used to generate bit-true test vector for RTL level design(FPGA). ,802.11b simulink simulation source code for PHY layer. It can be used to generate bit-true test vector for RTL level d
sata_device_model
- sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
fpga
- fpga+sdram+PHY 芯片设计原理图-fpga+ sdram+ PHY chip design schematic
wp_wimax
- WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and t
TCPIPGuide_2-0_s9
- WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and t
m-mtip-10_100_1000_ethermac
- 10/100 0M以太网MAC解决方案，是IP核的相关说明，利用ALTERA的FPGA设计，QUARTUS软件为开发平台。-10/100/1000M Ethernet MAC solution is the IP core instructions, using ALTERA' s FPGA design, QUARTUS software development platform.
check_net_test
- 用来检查FPGA通过PHY发送数据时是否有掉帧的现象-FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of
MII
- 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
DM9000A
- DM900 100M物理层PHY芯片FPGA连接，fpga实现数据链路层功能，完成网络数据的收发-DM900 100M physical layer PHY chip FPGA connections, fpga data link layer, the completion of the network to send and receive data
usb_phy_latest.tar
- USB phy latest for design USB by FPGA
USB_fpga
- FPGA与USB PHY芯片Cy7c68013A通信的程序，Verilog语言-FPGA and USB PHY chip Cy7c68013A communication procedures, Verilog language
phyjingjian
- 通过fpga对phy芯片88e1111进行控制，可改变工作模式，传输速度等。-By fpga control of phy chip 88e1111 can change the working mode, the transmission speed.
DE2_NET
- DE2开发板例程源码，FPGA:EP2C35F256C6，代码基于quartus II 9.0以上的版本（随板光盘的为7.2的版本，在9.0以上的版本上编译通不过会报错）。该代码主要功能为FPGA对以太网通信，与PC机通信-In this demonstration, we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board. We use the
Zynq-Mini-ITX-Rev-E
- Zynq Mini-ITX 单芯片可编程SOC(ARM+FPGA)开发板电路原理图 -Zynq Mini-ITX Development Board Schematics the Zynq Mini-ITX development board features 2 GB DDR3 SDRAM, PCIe Gen2 x16 Root Complex slot (x4 electrical), SATA-III interface, SFP interface, QSPI Flash me
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man
100G以太网PCS子层研究及其在FPGA的实现
- 主要描述了100G以太网物理层在XILINX FPGA上的实现方式(100G Ethertnet PHY, XILINX FPGA, Vivado)
DBSTAR_RGMII
- Verilog实现的RGMII和GMII接口转接，适合适配不同PHY芯片接口使用(Verilog implementation of RGMII and GMII interface transfer)
rgmii_image
- 通过RGMII协议驱动的PHY芯片完成千兆以太网收发，包括ARP响应(With RGMII driving PHY IC to finish the internet communication)
802.11a PHY 代码
- 802.11a 物理层代码，采用verilog编写FPGA设计