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jiafaqi
- 实现四位加法器的VHDL代码，里面含有全加器的代码-achieve four Adder VHDL code, which contains the full adder code
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- 利用8279芯片实现通过2X8键盘输入加数和被加数并计算出结果，同时将加数、被加数和结果都在LED灯上显示出来。,Chip 8279 through the use of 2X8 and keyboard input addend addend and calculated results, at the same time, addend, addend and the results were in the LED lights on the display.
jiafaqi
- 实现一位全加器的运算，并通过调用模块实现四位全加器的运算-Implement a full adder operation, and by calling the module' s operation four full adder
jiafaqi
- EDA条件下乘法器的实现。AHDL语言实现输入显示乘法等功能-EDA under the conditions of the realization of multipliers. AHDL language features such as input showed that multiplication
jiafaqi
- Verilog 16位超前进位加法器源码-Verilog 16 bit CLA source
jiafaqi
- 哈尔滨工业大学计算机设计与实践实验，4位并行加法器-Harbin Institute of Technology computer design and practice of experiments, 4-bit parallel adder
jiafaqi
- 用Veriloge编的四位二进制加法器。用一个显示屏进行显示。-Veriloge series with four binary adder. With a display to display.
jiafaqi
- quartusii软件仿真实验代码 十进制加法计数器-quartusii software simulation code decimal addition counter
jiafaqi
- 能实现两个4位数的的加法运算，并显示两个加数和结果-To achieve two 4-digit addition operation, and displays the results of the two addend and
jiafaqi
- 计算机组成原理实验中加法器的verylog编程-computer
jiafaqi
- VFP环境下制作的简单实例。。。是一个加法器-VFP environment produced by a simple example. . . Adder
jiafaqi
- 加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。-Adder is generated and the number of devices. Addend and the summand input, and digital and carry the output device is a half adder. If the addend, the progress of summand bits
jiafaqi
- 可以实现几个数的相加的功能。是一个简单的c++的小程序。-Several numbers can add features. Is a simple small program c++.
jiafaqi
- 改程序实现了简单的加法器功能，很容易完成加法运算。-Reform program to achieve a simple adder function, it is easy to complete the addition.
jiafaqi
- 使用硬件描述语言设计的加法器，现代逻辑器件-Hardware descr iption language design adder, modern logic devices
jiafaqi
- 数字系统设计及VHDL实践半加器与全加器源代码-half-adder and full-adder
jiafaqi
- 利用FPGA，VHDL设计一个加法器控制LED。-The use of FPGA, VHDL design an adder control LED.
jiafaqi
- 用VHDL语言实现对FPGA的程序编写，实现加法器功能。-FPGA program written using VHDL adder function.
jiafaqi
- 加法器 使用java代码编写简单的加法运算器 适合初学者-Adder suitable for beginners to use Java code to write simple adder
jiafaqi
- 计时器 用来简单的计时，类似于平常生活中用的秒表等计数器-Timer is used to simple timing, similar to ordinary life with the stopwatch counter