搜索资源列表
signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
CPU
- verilog编写CPU： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like CPU using verilog
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
mipsCPU
- MIPS CPU tested in Icarus Verilog
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
CPU
- mips系列，CPU的Verilog语言设计，自己写的-mips series, CPU of the Verilog language design, to write their own
MIPS_cpu_verilog
- 带流水线的类MIPS CPU verilog源代码-With lines of class MIPS CPU verilog source code
pipeline_code
- 实现了MIPS五级流水CPU,用verilog语言实现-MIPS CPU verilog
mips--cpu
- 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
mips
- mips verilog进行编写cpu,其中包括了若干的基本指令(use the verilog language to programme the CPU)
mips-cpu-master
- MIPS Implementation in Verilog. Full source code!
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
OpenMIPS
- 《自己动手做CPU》书后源码 包含各章节实例 分节使用(source code of mips CPU)
mips-cpu-master
- CPU设计，已通过模拟，有需要的自行下载吧(CPU design has been simulated)