搜索资源列表
FSM
- 这是用verilog硬件描述语言编的moore状态机代码-It is compiled verilog hardware descr iption language moore state machine code
moore
- moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
mealymoore
- verilog project for mealy and moore
Ch8_11
- this is a verilog program for a moore machine
Verilog_hw_problem2
- this is a verilog program for a moore machine
Moore_Asynchronous_state_machine
- moore异步状态机verilog实现，通过异步时钟和两个输入来对输出的状态进行控制，比同步状态机有更广泛的应用。-the moore asynchronous state machine verilog implementation, asynchronous clock and two input to the output state control, have a much wider application than the synchronous state machine.
t2_manchester_coder
- Manchester 编码器的Verilog与VHDL实现，并分别采用moore和mealy机对其进行描述，比较了两种实现方法的不同。并且每种情况都给出了测试脚本，希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And
Ver_prog
- Verilog programs for trafficlight controller, dicegame, mealy,moore machines and universal shift register
user_encoded_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
safe_state_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
soda_machine_mealyamoore
- soda_machine的一个有限状态机，用verilog描述，分别有moore和mealy,还提供了testbench.-soda_machine of a finite state machine, with verilog descr iption, respectively, moore and mealy, also provides a testbench.
verilog
- moore逻辑实现，用verilog完成，在multisim上完成(moore logic realization)
4bit_moore
- Moore machine is state machine whose output is a function of only the current state.