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cf_fp_mul_p_5_10
- verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
cf_fp_mul_p_8_23
- verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
add.rar
- 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）,Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
PipeLine.tar Verilog实现MIPS五段流水线
- Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
64point_FFT
- 64-point Pipeline FFT，包含Verilog语言编写的64点FFT运算rtl级程序以及测试程序，此外，还包含设计文档。-64-point Pipeline FFT, Verilog language includes a 64 point FFT computation rtl-level procedures and testing procedures, in addition, includes the design documents.
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
H264
- h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
MIPS
- 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
cordic
- vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
cordic-verilog
- 用Verilog写的cordic相位鉴别，采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
Report RISC in Verilog
- Report RISC in Verilog.16-bit. 5-stage pipeline
CPU-Pipeline
- 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)