搜索资源列表
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
lab4
- ics lab4 (csapp lab4) Software School, ICS, Autumn 2010 Optimizing the Performance of a Pipelined Processor-ics lab4 (csapp lab4) Software School, ICS, Autumn 2010 Optimizing the Performance of a Pipelined Processor
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
FFT
- 流水线模数转换电路输出信号做fft后求SNR,SNDR的matlab程序-matlab fft program for SNR and SNDR of pipelined analog to digital converter（ADC）
pipeline_10b_adc
- 10bit pipelined adc in matlab
SNDR-test-for-pipelined-ADC
- 流水线ADC信噪比测试程序,最后一级flash位数可调，可进行SNDR和SFDR的测试-SNDR test for pipelined ADC
3-10-bit-pipeline_10b_adc
- model simulink of 10 bit pipelined adc
mips_multi
- mips processor multicycle non-pipelined microprocessor by verilog
file_encryption
- AES分组加密算法做的文件加解密演示, 采用多线程流水线方式对文件进行 读->加密/解密->写 操作.-AES block cipher algorithm for encryption and decryption so the paper presentations, the use of multi-threaded pipelined read on paper-> encryption/decryption-> write operation.
Pipelined_Implementation_of_Baseline_JPEG_Encoder
- Pipelined Implementation of Baseline JPEG Encoder
liushuixian_mul
- 流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
cordpipe
- pipelined cordic algorithm in hdl
adc
- 1.5-b/s Pipelined A/D behavior model 以及功能包,包括SNR INL DNL测试- 1.5-b/s Pipelined A/D behavior model Include SNR INL DNL test progrems
pipeline_6bADC
- 6bit pipelined adc in matlab
ps2lab1
- pipelined CPU with hazards and forwarding unit
Pipelined-and-Parallel-Recursive-and-Adaptive-Fil
- Pipelined and Parallel IIR Recursive and Adaptive Filters design for hardware implementation
4-10-bit-Pipelined-ADC-Model
- model non linear of 10 bit Pipelined ADC
lesson6_pipelining
- Analysis of the MIPS 32-bit, pipelined processor using synthesized VHDL
Pipelined-ADC
- pipelined ADC, 各种参数可调，最后包括fft分析和整个传输曲线-pipelined ADC, adjustable parameters, and finally including the entire transfer curve analysis and fft
pipelined-CPU
- 流水线CPU的设计，计算机组成原理与系统结构的实验做的-The design of the pipelined CPU