搜索资源列表
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
Syn_FIFO
- 一个可综合的同步FIFO的verilog源代码
syn_fifo
- Synchronous FIFO 用來處理synchronous clock domains間的傳輸
syn_fifo
- A Verilog descr iption of a synchronous FIFO memory circuit
syn_fifo
- Synchronous FIFO (one clock)
syn-fifo-verilog
- 用verilog语言写的同步FIFO设计源代码。-The source codes for syn-fifo using verilog language.
syn_fifo
- 很好的同步FIFO设计代码，和大家分享一下，多多交流，不是我自己写的-Good synchronous FIFO design code, and share with you some more exchanges, not my own writing
syn_fifo
- 同步FIFO的源代码（单时钟），使用SystemVerilog语言实现-Synchronous (single clock) FIFO，using SystemVerilog
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
Syn_FIFO
- 在libero环境下，FPGA如何使用ProASIC3/E的同步FIFO-In libero environment, FPGA using ProASIC3/E of the synchronous FIFO
syn_fifo
- synchronous fifo. This is a fifo code of a synchronous fifo.
Syn_FIFO
- 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
syn_FIFO
- 同步FIFO，主要用于数据缓存，给异步FIFO打下基础，是个不错学习例子，在ncverilog中仿真通过-Synchronous FIFO, mainly used for the data cache, and lay the foundation to the asynchronous FIFO, is a good example of learning through simulation in ncverilog
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
Syn_FIFO(wanzheng)
- 基于IPcore的同步FIFO的编写。读写数据位宽都为8bit，深度为32.-Based IPcore synchronous FIFO preparation. Read and write data width are 8bit, a depth of 32.
syn_fifo
- 关于FPGA同步FIFO和异步FIFO的编写和设计方案-Writing and design on FPGA synchronous and asynchronous FIFO FIFO
syn_fifo
- Verilog，syn_fifo ，内含详细说明，同步FIFO为TPRAM-Verilog, syn_fifo, containing detailed instructions for synchronous FIFO TPRAM
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
syn_fifo
- 该源码包是同步fifo的Verilog语言模型，主要包括2个部分：同步fifo控制模块、测试文件。(The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.)
syn_fifo
- 读写控制器，带满和空指示，拿出来和大家分享(Read-write controller)