搜索资源列表
USB2_chip
- USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
USB2.0IP_core_Verilog
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
usb_phy
- umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
usb_2
- usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
usb_funct
- usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件
USB2.0IP.rar
- 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档,Complete Verilog language developed by USB2.0 IP core source code, including documentation
CY7C68013.rar
- USB2.0的Verilog实现，含有完整的FPGA代码,Use Verilog to implement the USB2.0 protcol
USB2.0-IP-core
- 用verilog 写的USB2.0，含源码。从别处找来的，不敢独享，希望对大家有帮助-Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help
VERILOG-USB2.0IP-core
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
USB2.0IP(RTL)
- USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
USB2.0
- usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
usb20
- 通用接口usb2.0的verilog开发代码-Common interface usb2.0 development of the verilog code
usbtrace[1].v1.1
- usb2.0 trace verilog code very useful
usb2.0-verilog-hdl
- usb2.0协议层的verilog hdl实现-usb2.0 protocol layer implementation verilog hdl
verilog-usb--protel-design
- 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
usb2.0_funct_ip
- 一个USB2.0的IP核（详细verilog源码和文档），很不错的参考设计-A USB2.0 IP core (for details verilog source code and documentation), it is a good reference design
USB2.0
- 完整的用VERILOG语言开发的USB2[1].0 IP核源代码，包括文档、仿真文件-USB2 module
USB2.0的IP核（详细verilog源码和文档）
- USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
13_usb_test
- fpga usb2.0 cy7c68013 黑金的板子(fpga usb2.0 cy7c68013)
FPGA_USB2.0设计
- 把FX2配置成从FIFO的模式， 配置为单片机工作时钟24M，端点2输出，字节1024，端点6输入，字节1024，信号全设置为低电平有效等。我们的模块驱动时钟我们配置成内部输出时钟，也就是让FX2给我们的设计当做时钟源，输出一个最大的配置时钟48M的时钟。(The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input