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Triggersignalaccuratedataacquisitionsystemdesignde
- 在一些系统中，经常用到对触发信号延时一段时 间后，再对某些目标信号进行采集，通常这段延时要求 非常精确，还要做到范围可调，一般这种延时的最小时 间单位小于100ns。如果选用普通微控制器，延时系统的操作界面比较容易实现，但是靠软件延时得到结果的准确性较低。考虑到芯片功能、开发环境以及接口方便等问题，最终选用一片常用的AlteraSVCPLD EPM7128SLC3411]作为系统的核心控制部分，来实现 信号延时、输人设定、运行显示的功能。应用Veril- o苦2〕语言，在
SD_verilog.用了硬件描述语言Verilog在完成对SD卡控制器的编写
- 该代码，只用了硬件描述语言Verilog在完成对SD卡控制器的编写，经济实用,The code, only the hardware descr iption language Verilog in the completion of the SD card controller to prepare, economical and practical
DataSort.rar
- FPGA内，通过Verilog语言，实现冒泡法数据排序。仅供参考！,FPGA, through the Verilog language, implementation data bubble sort method. For reference purposes only!
用verilog写的对ad0809的控制
- 用verilog写的对ad0809的控制，完整工程，希望对大家能有帮助,Written using Verilog for ad0809 control, complete works, in the hope that we can help
AD.FPGA控制AD7321的模块
- FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档。,FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.
ds18b20.ds18b20的Verilog程序
- ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。,ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor.
LCD.基于FPGA的LCD1602驱动
- 基于FPGA的LCD1602驱动，verilog代码，已经调试成功,LCD1602-driven FPGA-based, verilog code debugging has been successful
MiniStep.rar
- XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创,XC95144 stepper motor drive source, using verilog vhdl development, personal originality
(fpga)sdram.rar
- verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件,Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
accumulator.rar
- 实现累加器的verilog源码，广泛应用在通信电路设计中,The realization of accumulator Verilog source, widely used in communication circuit design
vcs_simulation_mannual(Edition
- VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.,VCS-verilog compiled simulator is the Synopsys company s products. Its simulation at a fairly rapid pace, and support multiple call mode. This document is a good guide.
ISA.rar
- pc104代码，这是本人调通过的。标准ISA通信接口，用VHDL编写,pc104 code, This is my tune adopted. ISA standard communication interface, using VHDL prepared
sync(shipintongbuxinhao).rar
- 基于QuartusII环境下以模块化的形式做成的视频复合同步信号。,QuartusII-based environment to create the form of modular composite video sync signal.
Altera_8051_IPcore_v1.2.rar
- Alera 的8051 IP core的示例文件5个,Alera the 8051 IP core of the sample file 5
VHDLRS232_RS422.rar
- VHDL写的RS232和RS485通信代码,很基础的一个工具,VHDL written RS232 and RS485 communication code, it is a tool based on
dds(heli).rar
- DDS用verilog 实现，可以实现方波、正弦和三角,DDS using verilog realized, can be square wave, sinusoidal and triangular
xapp460.zip
- 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）,Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
dacconf.rar
- 通信中常用的AD9857芯片的FPGA配置源码VERILOG实现,Communications commonly used in the AD9857 chip FPGA realization of VERILOG source configuration
DDS.rar
- FPGA控制AD9854的源文件，verilog，附有简单文档。,FPGA to control the AD9854 source file, verilog, with a simple document.
MT29FxxG08xx.rar
- MT的NAND FLASH MT29FxxG08xx系列的Verilog仿真模型，包含详细说明，试验证明，非常准确。,MT of the NAND FLASH MT29FxxG08xx series of Verilog simulation model, contains a detailed descr iption, testing proved very accurate.