搜索资源列表
I2S
- 用verilog实现的 I2S 源码，可以直接通过Quartus运行-I2S implementation by verilog source code can be run directly through the Quartus ~ ~
i2s_rel1_2
- I2S verilog HDL code including test environment
spitoi2s3
- spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
SPItoI2S
- 该文件是I2S 转 SPI的Verilog的源代码，可以在此基础上修改成自己的应用代码-The file is transferred SPI, I2S Verilog source code, you can change the basis of their application code into
Verilog_cpu-_example
- 想用verilog进行CPU搭建的同学过来围观啦~-Want to use verilog for students to build over the crowd CPU 啦 ~
I2S
- 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
iis
- I2S RTLs 很好的程序,已经成功通过验证和测试-I2S verilog RTLs, very easy to read
I2S-Serial-communication
- 这是I2S总线接口的Verilog实现源代码，包含了计数、左右通道选择、串行转并行等功能。-This is a Verilog I2S bus interface source code, including the count, about channel selection, serial to parallel functions.
i2s_input
- 基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真-FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment
i2s_dome2
- 音频接口I2S的Verilog实现， -Audio port of Verilog
i2s
- 用Verilog实现的i2s功能，支持24bit的左右声道 接收和发送。左对齐，延迟1拍。(I2S module, Verilog I2S, up to 24-Bit Data Data Valid on Rising Edge of SCLK)
i2s_top
- i2s接口fpga实现，工作在主模式，ISE和vivado下已验证(I2S interface FPGA implementation, working in the master mode)
i2s_interface
- verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)