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miaobiao 用verilog VHDL描写的秒表程序
- 用verilog VHDL描写的秒表程序，可以显示百分秒，秒和分。-Verilog VHDL with the descr iption of a stopwatch program, can display the arc, seconds and points.
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- verilog写的分频程序,可以对输入的频率分频-Verilog write the sub-frequency procedures, can the frequency of the input frequency
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- 用Verilog HDL编写的秒表设计，可以实现百分之一秒，十分之一秒，秒，十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
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- 秒表功能，自带工程，EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
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- 用VERILOG实现秒表的开发设计，(1)熟悉按键扫描、按键防抖和数码管驱动接口电路原理；(2)掌握按键扫描、按键防抖和数码管驱动接口电路设计开发；(3)掌握状态机实际应用设计。-To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital control key driver interface c
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- 秒表实验verilog代码，我已经调试好。希望供大家学习使用。-clock using counter code of verilog HDL.I debug it right
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- 秒表 数码管显示 采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
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- verilog 的 48M频 出入秒表，带停止启动 清零功能-the verilog of 48M frequency of access stopwatch, with stop start clearing the
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- 这是用verilog写的一个关于秒表实现的程序，已在DE2上成功实现-Verilog write a stopwatch to achieve the program has been successful on the DE2
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- 基于Max+plus2软件的Verilog VHDL语言的按键控制数码管显示秒表-Based on Max+plus2 software Verilog VHDL language button control digital display stopwatch
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- 用verilog语言在FPGA上实现秒表数码管显示-Implemented on FPGA using Verilog language stopwatch digital display
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- 由verilog编写的秒表程序，按键控制 按下一键秒表停止 按下另外一键 秒表又运行-Verilog prepared by a stopwatch program, press a button control key pressed another button to stop the stopwatch stopwatch and run
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- 一个精确的秒表，显示在数码管上。对于初学者使用verilog有很大的帮助，同时注释很详细。-An accurate stopwatch displayed on the digital pipe. For beginners verilog a great help, and very detailed notes.
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- 基于fpga的多功能数字时钟 在数码管显示 verilog语言编写 可实现校时 暂停以及设定闹钟的功能-FPGA time clock
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- 在Quartus II 环境下利用Verilog语言编写的秒表程序，包含模块化器件和仿真波形-In the Quartus II environment, use Verilog language stopwatch procedures, including modular devices and simulation waveforms
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- 用硬件描述语言Verilog HDL完成秒表设计模块，使用数码管。-Using hardware descr iption language Verilog HDL to complete the stopwatch design module, using digital tube.
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- 秒表数码管实现，通过仿真验证，已下载到板子验证(The realization of the stopwatch digital tube)