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Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
sdram-control-verilog
- SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.
readmemh
- Verilog使用readmenh()的範例-Verilog using readmenh () example
sgs32
- Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable d
32bitcpu
- 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations righ
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
RISC-CPU
- 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。 程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
crc_verilog_xilinx
- 包括下面文档： readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. cr
verilog-axi-master
- Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi