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VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
8_LigWater
- FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序-FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !
vhd_divider
- lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器-lattice isplever7 Treasury did not divide, so the Internet to find a foreigner to write the VHDL divider
divide
- 除法器-Divider
cordic
- cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root a
CLK_DIV
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
cpu
- 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the f
f
- This documents describes a free single precision floating point unit. This floating point unit can perform add, subtract, multiply, divide, integer to floating point and floating point to integer conversion.-This documents describes a free sing
VHDLfenpin
- VHDL进行分频的完备资料,包含偶数、奇数、小数、分数-VHDL for the completeness of the information divide, including even and odd numbers, decimals, fraction
clk_div
- 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
exercicio4
- VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone -VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone II
GeneratingFPGA-AcceleratedDFTLibraries
- 关于DFT的文章，应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT
FJYFP
- 用vhdl语言编写的分频程序，一个50分频，一个100分频，一个19200分频-Written by vhdl divide program, a 50-band, a 100 frequency, a frequency of 19200
The-way-of-divide-and-hex
- 这个文件中介绍了分频和各种进制编写的几种方法，VHDL语言，-This file is described in several sub-frequency and a variety of hex write the VHDL language,
VHDL-counter
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。 下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。 -In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the c
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
VHDL
- 正弦波发生器代码VHDL 其中包括分频 正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
Prescaler-to-use-VHDL-design
- 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, i
fp
- 通过quartus2软件使用VHDL语言将输入频率分频的程序(divide the frequency)