搜索资源列表
divider
- 16位有符号整数除法，将商并入移位后的被除数，节省资源。-16-bit signed integer division, will shift into business after the dividend, saving resources.
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
VHDL
- VHDL的4bit*4bit的有符号无符号的乘法除法实现-VHDL unsigned signed to achieve the multiplication division
4multiplier
- 4位乘法器vhdl程序-- DEscr iptION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure
FPGArealiztionofdigitalsignalprocessing
- 数字信号处理FPGA实现 实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHD
convolution_calculator_4_bits
- convolution is important and is widely used in digital signal processing.For example, in LTI system. Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.
fix2float_signed
- VHDL语言，有符号定点数转化为浮点数，Pavle Belanovic教授编写-Conversion from signed fixed-point to floating-point representation
signaddsub12
- vhdl coding for signed adder substractor
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
12bitMulti
- 用VHDL编写的有符号的12位乘法器，编译通过，仿真正确，FPGA开发板上用过的。-Prepared using VHDL signed 12-bit multiplier, compile, correct simulation, FPGA development board used.
arith_lib2
- This a VHDL library which performs signed digit operations in VHDL.-This is a VHDL library which performs signed digit operations in VHDL.
mul32
- 32位无符号乘法器 采用VHDL语言编写，很容易改为有符号32位乘法器-32-bit unsigned multiplier using VHDL language, it is easy to signed 32-bit multiplier
Multiplieur-signe
- VHDL code of a signed mixer with a testbench !
cheng
- 5位带符号的乘法器设计，语言VHDL，课设必备-5 signed multiplier design, VHDL language, class required
new_yasodai_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
Jammuna_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
zhaoyueyue2xiugai
- 4位有符号数除法，vhdl语言编译，可实现有符号数的除法-4 signed division
E3_1
- 测试有符号和无符号二进制数相加结果对比，并对结果进行sim仿真(Test, signed and unsigned binary number addition, result comparison)
cnt8updown
- 8位上下同步计数器 适宜小型练手操作 易于理解(an 8-bit up and down synchronous counter in VHDL with the following features: (1) The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered (three-state). (2) The counter is