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watch
- 用FPGA实现带马表日历的电子表，verilog代码。
watch
- 基于verilog-HDL的电子秒表电路，采用quartusII72编译仿真，经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
watch
- 基于quartus II软件 用verilog 语言描述的一个秒表-quartus II verilog
clock
- 实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
Watch
- Design Watch with set time by Verilog for kit DE2
DigitalWatch
- Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
foundatonise
- WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256 -6) -WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256-6)
watch(2)
- digital watch : verilog source code
watch
- 懂哥作品 用verilog编写的，我没试验呢开发板没有-verilog watch made by dongge
FPGA_A.Thien
- stop – watch (verilog)
watch
- verilog 完全集合了电子表所拥有的功能，计时，调时，秒表，闹钟四个功能-verilog completely owned by a collection of spreadsheet functions, timing, tone, the stopwatch, alarm clock features four
clock-design-verilog-Fpga
- verilog设计的计时表，数字电路设计，FPGA-using verilog design watch, digital circuit design, FPGA
digital_watch
- Verilog code of digital watch
stop-watch
- stopwatch with verilog it counts up and reset
final_lab5
- Verilog code for stop watch
watchdog
- 针对低功耗和低频率的看门狗设计verilog代码-watch dog design code
stopwatch
- 基于Verilog的秒表设计，可以在modelsim与开发板环境中正常运行。-A stop watch program based on verilog
clock
- Clock generator code in Verilog for Stop Watch
watch_dog
- verilog实现watch dog看门狗功能。(watch Implement watch dog function.)
verilog-stopwatch-master
- verilog stop watch code for end user