资源列表
lab10000
- detection of the following sequence ‘10110110’in VHDL
cout60
- 用VHDL语言编写的60进制计数器，初学者使用-VHDL language with the 60 binary counter, for beginners to use
12dac
- 自己编的12位dac 不过需要外接滤波器才可以看得更好些-a 12bit dac need a lpf which can view clearly
ringcounter
- ring counter for vhdl code
E1-Program_With_Functions
- exercise lab for students
FFT
- FFT在NIOS2上的的实现。通过AD给的值。-In the NIOS2 FFT realization.Through the AD to value.
dp
- datapath code in verilog for pipeline processor
generator
- generator of functions for vhdl
booth_mul
- 乘法器 基于改进booth编码 已验证 clk-multiplier modified booth
mc
- 可控脉冲发生器:采用1KHz的工作时钟，初始化周期为2.5s，占空比为50 ，所以周期（T）初始化为2500，占空比（Result）初始化为1250；用按键S1、S2、S3、S4分别实现周期增大、周期减小、占空比增大、占空比减小。-Controllable pulse generator
simple_ram
- the file about simple ram by VHDL code
fulladdr
- full adder source and test bench 5