资源列表
Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
RISC8.ZIP
- verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
ads7822
- ads7822的verilog驱动 fpga芯片为altera公司的ep2c35， 程序调试过好使-ads7822 of verilog-driven
16QAM
- 基于FPGA 16QAM解调verilog代码，-16QAMdemoluator veriliog
SDRAM_ipcore_
- Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
TLC2543
- 使用Verilog实现的AD采样，很有用的！-Implemented using Verilog AD sampling, very useful!
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
Verilog-float-mutiplier
- 32位浮点型乘法器，和开方器,很有用的一种，就是认真读懂-32 float mutiplier
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
ssram
- 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
caiheng
- 利用Verilog实现32位浮点数的乘法,并且已通过验证.-Using Verilog to achieve 32-bit floating point multiplication, and has been verified.
dpll
- dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.