资源列表
1
- 基于matlab和QuartusII开发的无线通信FPGA设计,内有(matlab代码,Verilog代码,缩略语表.doc)注释详细,代码数十个,总有一个是你喜欢的!-Matlab and QuartusII based on the development of wireless communications FPGA design, there are (matlab code, Verilog code abbreviations. Doc) Notes detail dozens of
NCO_based_rom
- 完整的基于ROM查找表的NCO 产生10位宽的正交信号-Integrity of the ROM-based lookup table of the NCO have 10-bit wide of the orthogonal signal
xilinxfpga_jtag
- XilinxUSB EEPROM是xilinx usb下载线的EEPROM程序，可以用来做xilinx的usb下载线-XilinxUSB EEPROM is xilinx usb download cable in the EEPROM program can be used to make the usb xilinx download cable
Core8051
- VERILOG编写的Core8051实验例程，包括整个工程，周立功公司提供-VERILOG Core8051 written test routines, including the entire project, provided ZLG
cic
- altera 公司 quartusII 提供的cic ip ,文件版本是8.0-altera company quartusII provided cic ip, file version is 8.0
nnARM_core
- nnARM核源代码,用verilog编写,请需要的朋友下来研究,不要用于商业用途-nnARM core source code, using verilog write, please study the needs of a friend down, not for commercial purposes
ALU
- ALU与ALU控制器设计，verlog语言书写-ALU
mult
- 16位乘法器,输入16位乘数，输出32位积，采用循环移位算法-a multplier
counter
- 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
application_selector
- NIOS II 内核 程序选择器程序 包括硬件程序及软件程序-NIOS II core program selector program, including hardware and software programs
sobel
- Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现-Verilog，Sobel Operator
CPU
- 用VHDL编的简易16位和8位CPU，可完成加减乘法移位等功能，拥有源码和设计文档，资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete