资源列表
CLOCK6
- 基于SPARTAN-3E的数字电子时钟，采用1602LCD液晶显示屏显示，可显示时分秒。-SPARTAN-3E-based digital electronic clock, using 1602LCD LCD display, can display minutes and seconds.
resolutionquartusII
- 用verilog编写的分辨率提高的源代码 采用双线性插值-Written resolution with the verilog source code to improve the use of bilinear interpolation
uart
- uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus
TestLED2C5
- 文件中有CPU8051V1.vqm具体使用的例子和CPU8051V1.vqm文件，适用于quartusii软件中对单片机的嵌入练习和使用-CPU8051V1.vqm document specific examples of the use of CPU8051V1.vqm documents, quartusii software for single-chip embedded in the exercises and the use of
fpga_ads8364
- fpga控制ti的多通道高精度ad芯片ads8364的verilog源码-fpga multi-channel high-precision control ti ad-chip ads8364 the verilog source code
DDR_FLASH_VHDL_Verilog
- FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
hamming
- 汉明码编码与译码全过程，经过验证，简单实用-Hamming code encoding and decoding the entire process, proven, simple and practical
ZNYB1
- CPLD测方波频率和占空比的Verilog代码-CPLD mearsure Verilog
quartus-11.0-crack
- quartusⅡ+11.0破解器,最新版quartus破解软件，可用。-quartus Ⅱ+11.0 cracker
bayer2rgb
- bayer到RGB， 12bit进，24bit出，实验效果很理想，简单易用 -bayer to RGB, 12bit entry, 24bit out of the experimental results is very satisfactory, easy to use
verilog--maopao-paixu
- 用verilog实现的冒泡排序法 ，有testbench-Implemented using verilog bubble sort, there is testbench